Rosepoint chip (via Intel)

‘Fused’ chips are fast becoming the status quo in powering today’s mobile devices, particularly tablets and smartphones. For those of you who don’t know what fused chips are, they combine CPU’s and  For those of you who don’t know what fused chips are, they combine CPU’s and GPU’s on a single chip (or die) such as AMD’s Fusion. Intel has recently stepped up their game in this field with the introduction of their Sandy Bridge line of fused chips, but they have not stopped the integration there.

The company has recently stated that they have combined Wi-Fi with their line of Atom processors code named Rosepoint which will be unveiled at this year’s International Solid-State Circuits Conference in San Francisco. Not much is known about Rosepoint but a few ‘leaked’ images and a vague Intel press release. Details say that it features a 32nm SoC with a built-in Wi-Fi transceiver (running at a reported 2.4 GHz or 4G) with two Atom CPU’s all crammed onto the same die. Another goal is to reduce the chip-count. Although a wireless transmitter that close to other digital signals would cause interference, Intel has found some "hush-hush" way to shield the CPU from the WiFi onboard. The integration of wireless onto CPU cores means less power usage as well as costs. If all goes well, the technology could be found in mobile devices as early as 2013.

More information will be released at this year’s ISSCC so check back for an update! (ISSCC runs from February 19-23rd.)

Cabe

http://twitter.com/Cabe_e14

Picture concept from Intel's patent US 2011/0277023

Intel has patented an idea that would allow Wi-Fi devices to connect to their router simply by sounds. Televisions and other devices have lengthy codes which must be added to the router’s list to ensure a secure connection. However, entering this code can be time consuming and a challenge for people that are visually or physically impaired, so instead, the Intel team has proposed a future change to the Wi-Fi Protected Setup.

This change comes in the form of Wi-Fi devices that use sounds as authorization ID codes to allow connectivity between the device via a microphone-equipped router. The team says that the sound could be anything from arranged clicks, to music or even a synthesizer voice as long as it is unique to the device attempting to connect, effectively replacing its printed ID code.

Of course, security issues could arise if the sound is heard by people who should not have access to the router. One of their main development goals will be to assure the sound does not penetrate walls. If the project proves to be secure, Intel hopes to change the standard Wi-Fi Protected Setup now used by Wi-Fi routers. (Ultrasonic is always an option.)

Cabe

http://twitter.com/Cabe_e14

Engineering On Friday takes on the possible use of Sound-WiFi

Intel-Micron 20nm NAND memory at 128Gb (via Intel)

A joint Intel-Micron project brings 128Gb of data in a fingertip size package. The team is boasting the possibility of a Terabit through stacking 8 of these chips. Micron's development venture IM Flash Technologies (IMFT) brings the industry's first 20nm NAND memory fabrication using a planar cell structure. The technique brings unprecedented scaling due to the first use on Hi-K/metal gate stack on NAND memory. The tech is capable of 333 MT/s (megatransfers per second.) To get an accurate bit transfer rate we would have to know the bus length. Intel stated that the NAND memory meets the ONFI 3.0 specification for high speed NAND memory, which means up to 400MB/s. (Just a ball-park figure.)

Hi-K is in reference to a material with a high dielectric constant "K" in comparison to silicon dioxide. In other words, the ratio of  the amount of electrical energy stored in the material by an applied voltage in relation to that stored in a vacuum. When scale goes below 2nm, silicon dioxide tends to leak current due to tunneling, leading to power inefficiencies. A high-k material replaces less than 2nm scale gate material and allows for increased gate capacitance without leakage. Intel toyed with hafnium-based high-K materials for gate replacement on 45nm tech back in 2007. Intel predicted that use of such material will aid in continuing Moore's Law.

A 64Gb version of the tech is already on the market with 128Gb planned for availability in January 2012. Carrying one's entire digital life with them, discretely, at all times does not seem out of the realm of possibility.

Why stop at high-k replacement, go to 3-atom thick molybdenite.

Cabe

http://twitter.com/Cabe_e14

Intel has moved from planar transistors to, 3D, tri-gate transistors. This allows for the increase of speed, reduced power consumption (50% at constant, 37% in low voltage conditions), and of course performance and efficiency. Intel found that shrinking to 22nm did not meet Moore's Law expectations, but changing the individual transistor functions was the only way to meet the goal. Estimates bring the manufacturing costs of the tri-gate to 2-3% over current silicon-wafer construction. The 3D transistor processor, codenamed Ivy Bridge, will go into production and distribution in the second half of 2011. 14nm and 10nm chips with 3D transistors are being planned for 2015. Intel states that this tech is not limited to the cutting edge, so we will see wide adoption of the technique across Intel's product families.

I included the above video for  Mark T. Bohr's deadpan performance. He made the corny jokes in the video, acceptable. Like the tri-gate transistor, that is a commendable achievement in itself.

Eavesdropper