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PLD Device Overview
ABSTRACT
This article is the first section in the FPGA and CPLD Guide series and provides an overview on the major features of the PLD devices with emphasis on concepts, classifications and features of the PLD devices, including their basic framework, design flow and common development tools.
Concepts of PLD devices and their classifications
What are PLD devices and their classifications?
Digital integrated circuits have run to the ASIC step by step up to the present with the development of the micro-electronics design technology and process. However, many limitations (such as too long design cycle, bad flexibility and too much devotion for correcting PCB, etc.) narrow down their application range. So, Hardware engineers were trying to find a new flexible design technique so that they can design and modify large scale digital logic and develop ASICs for R&D purpose. All of these are the basic ideas for the PLDs.
Generally, PLD means digital integrated circuits whose internal combination architecture and logic elements could be modified and configured by software means in order to get the established functions and its full name is Programmable Logic Devices. These PLDs can be classified as PLA (Programmable Logic Array), EPLD (Erasable Programmable Logic Device), SPLD, CPLD and FPGA.
Concepts and Features of SPLDs, CPLDs and FPGAs
Concepts and Features of SPLDs
SPLD is the abbreviation of Simple Programmable Logic Device which includes GALs and PALs. GAL means the Generic Array Logic and PAL is the Programmable Array Logic. GAL and PAL are inchoate forms of PLD. Most of SPLDs are manufactured by E2CMOS process. SPLDs have simpler architecture and lower programmable elements density. Most of their programmable logic elements are –AND array or –OR array and used to design some types of simple digital logic circuits. Moreover, they have many advantages such as low power, low cost, small package, high reliability, easy to design, programmable by software means and modifiable, etc. So, SPLDs are suitable for devices sensitive to cost, usually used as simple digital logic to replace 74 series logic chips.
Concepts and Features of CPLDs
CPLD is the abbreviation of Complex Programmable Logic Device. Most of CPLDs are based on Product-Term architecture and manufactured by E2CMOS process and a few of them are based on the Flash process, EEPROM process or Anti-Fuse process. Comparing with FPGAs, they have many disadvantages including simpler architecture, lower programmable elements density, fewer Flip-Flops, limited layout resource and simpler logic functions.
However, CPLDs have its advantages such as lower cost, lower expense, better security, and easy design and debug benefited from their fixed Pin to Pin delay. Moreover, they have more improvements in performance and can be used to design more complex and faster logic functions comparing with SPLDs. Generally, CPLDs are used to implement the combinatorial logic design.
Concepts and Features of FPGAs
FPGA is the abbreviation of Field Programmable Gate Array. Most of FPGAs are based on LUT (Look-Up-Table) architecture and manufactured by SRAM process and a few of them are based on the Flash process, EEPROM process or Anti-Fuse process. Comparing with CPLDs, they have many advantages including more complex architecture, higher programmable elements density, more Flip-Flops, abundant layout resource and more complex logic functions.
However, FPGAs have its own disadvantages such as higher cost, costly expense, less security, and hard to design and debug resulted from their uncertain Pin to Pin delay. Certainly, their performance is better and can be used for designing more complex and faster logic functions comparing with CPLDs. Generally, FPGAs are used to implement very complex combinatorial logic and Timing logic design and are ideal for high-end digital logic circuit design and digital IC design with high speed and high density. FPGAs are the sources of all the digital integrated circuits design and we can get everything within our ability with FPGA.
CPLD’s Basic Framework
What is the basic framework of CPLD? First of all, CPLD is based on the Product-Term architecture. The Product-Term is the output of –AND arrays in the MCs. In fact, Product-Term array is a “AND-OR” array, every junction is a programmable fuse. A –AND logic is implemented if a junction is connected. Generally, there is an -OR logic behind –AND logic to implement the –OR logic relation in the minimum logical expression. “-AND” and “-OR” arrays work together so that they can implement the complex and combined logical functions. The principle of Product-Term architecture is shown as below.
The principle of Product-Term architecture
Next, CPLD’s basic framework is relatively simpler comparing with FPGA and made up of programmable I/O units, basic logic unit, routing pool and assistant functional modules, etc. CPLD basic framework is shown as below.
CPLD basic framework
Programmable I/O units are used to drive and match I/O signals under the different conditions of electric characteristics. CPLD’s programmable I/O units can only support a few of I/O standard and their frequency is comparatively low. Basic logic units in the CPLD are called Macro Cell (MC) and they are the main body of CPLD. MCs are used to implement different types of logical functions by different configurations. The Macro Cell is actually made up of some AND arrays, OR arrays and Flip-Flops. “AND-OR” arrays are used to implement combined logical functions and Flip-Flops are used to implement timing logical functions. The scale of device is indicated by the number of MC. An example about MC’s architecture is shown as below.
MC’s architecture
Centralized routing pool architecture is adopted in CPLD. The routing pool is a Switch Matrix in nature and used to interconnect the output and the input among different MCs by connecting junctions. Because routing pool architecture in CPLD is fixed, the Pin to Pin delay, which is the standard delay from the input Pins to the output Pins in CPLD and represented as Tpd, is fixed. The Pin to Pin delay reflected the maximum frequency that CPLD can reach and clearly indicates the speed grade of CPLD.
FPGA’s Basic Framework
What is the basic framework of FPGA? Firstly, FPGA is based on the LUT plus Register architecture. The LUT is a RAM in nature. There are 4 inputs in a LUT in FPGA so far. So, every LUT can be looked as a 16x1 RAM with 4 Bits address bus. After the user described a logical circuit by the schematic or HDL languages, FPGA development software calculates all of logical circuit’s possible results automatically and writes these results into RAM in advance. So, that inputting a signal and carrying a logical value every time is equal to inputting an address and looking up the table, then finding the corresponding contents and eventually outputting the result. The principle of LUT architecture is shown as below.
The principle of LUT architecture
Secondly, FPGA basic framework is relatively simpler comparing with CPLD and made up of programmable I/O units, basic programmable logic unit, abundant routing resource, embedded block ram, bottom embedded functional units and internal embedded special hard core, etc. FPGA basic framework is shown as below.
FPGA basic framework
Programmable I/O units are the interface between FPGA and the periphery circuits and used to drive and match I/O signals under different conditions of electric characteristics. I/O units in most of FPGAs are designed as programmable pattern and suitable for different electric standards and I/O physical characteristics, which can adjust impedance characteristic, pull-down resistance, pull-up resistance, driver current, etc. The maximum frequency supported by the programmable I/O units is getting higher, and some high-end FPGAs can support data rate of up to 2GHz. Basic programmable logic unit in the FPGA are called LE by Altera, slice by Xilinx and PFU by Lattice, they are the main body of programmable logic, which are used to implement different types of logical functions by different configurations. The LE or Slice is made up of some LUTs and Registers. LUTs are used to implement pure combined logical functions, while Registers are used to implement synchronous timing logical designs. Generally, the configuration of classical basic programmable logic unit is a LUT plus a register. Scale of device is indicated by the number of LE, or Slice, or PFU, or usable logic gates. Examples about LE or Slice architecture are shown as below.
Stratix LE
LE in Normal Mode
Xilinx Slice Architecture
Routing resource architecture connects all the units in FPGA. The length and process determine the driving power and transfer speed of signals. Because routing resource architecture in FPGA is uncertain, the Pin to Pin delay, which is the standard delay from the input Pins to the output Pins in FPGA and represented as Tpd, is uncertain.
Embedded block RAM in FPGA can be configured as SPRAM, DPRAM, Pseudo DPRAM, CAM and FIFO. Bottom embedded functional units are those embedded functional modules which are used widely such as DSP Core and Nios/ NiosII Soft Core from Altera, Power Pc Core and MicroBlaze RISC processor Core from Xilinx, etc. All of these make FPGA can implement software and hardware associated system and become a design platform of high efficiency for SOPC step by step.
Common Development Tools for FPGA & CPLD
There are many EDA manufacturers offering development tools for CPLD for the user in the EDA field. However, Altera and Xilinx’s development tools are used most commonly for FPGA development.
Summary of Common Development Tools for Altera
Common development tools of Altera include QuartusII and MAX PlusII. QuartusII and MAX PlusII are integrated software packages or integrated development environment. QuartusII is mainly for the purpose of FPGA development and also support CPLD, while MAX PlusII is for FPGA development. QuartusII software supports nearly all of HDLs, while the early MAX PlusII software only supports AHDL.
There are many development tools integrated in QuartusII, including Mega Wizard, Schematic Editor, RTL Viewer, Assignment Editor, LogicLOck, PowerFit Fitter, Timing Analyzer, Floorplan Editor, Chip Editor, Programmer, PowerGauge, SignTapII, signalProbe, SOPC Builder, DSP Builder and software Builder, etc.
QuartusII supports multiform input modes, including Schematic input mode, HDL language input mode, IP Core input mode and other assistant input modes such as state machine input mode, wave input mode and true value table input mode, etc.
Summary of Common Development Tools for Xilinx
Common development tools of Xilinx refer to ISE basically. ISE is integrated software packages or integrated development environment. ISE is mainly for the purpose of FPGA development and also support CPLD. ISE software supports nearly all of HDLs.
There are many development tools integrated in ISE, including XST, Mega Wizard, Schematic Editor, RTL Viewer, Assignment Editor, LogicLOck, PowerFit Fitter, Timing Analyzer, Floorplan Editor, Chip Editor, Programmer, PowerGauge, SignTapII, signalProbe, SOPC Builder, DSP Builder and software Builder, etc.
ISE supports multiform input modes, including Schematic input mode, HDL language input mode, IP Core input mode and other assistant input modes such as state machine input mode, wave input mode and true value table input mode, etc.
Summary of Third Party Development Tools
The common third party development tools are synthesis and simulation software tools. Mainstream synthesis software tools include synplify/Synplify pro from synlicity, FPGA Compiler II/Express from Synosys and Leonardo Spectrum from Exemplar Logic. Mainstream simulation software tools including Modelsim from ModelTech, ActiveHDL from Aldec and Synopsys VCS/VSS from Synosys.
FPGA & CPLD Design Flow Brief Introduction
Generally speaking, the entire FPGA & CPLD design flow including circuit design and input, functional simulation, synthesis, post-synthesis simulation, implement, post-route simulation & validate, Board level simulation & validate & debug, etc. The complete FPGA & CPLD design flow is shown as below.
FPGA & CPLD design flow
Written by Arthur Zou
Sep. 19, 2008