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FPGA and CPLD Products
Abstract
This article is the second section in the FPGA and CPLD Guide series and will briefly introduce the major features of the CPLD and FPGA devices from Altera with emphasis on MAX II series, MAX3000A series, Cyclone II series, Cyclone III series, Stratix II series, Stratix III series and Stratix IV series, etc.
Brief Introduction for CPLD Products
Brief Introduction for MAX3000A Series
MAX3000A series CPLDs are high-performance, low-cost CMOS EEPROM-based programmable logic devices (PLDs) built on a MAX® architecture and are the mainstream CPLD product now. MAX3000A series CPLDs are manufactured through 0.3um CMOS process, with high-density PLDs that have 600 to 10,000 usable gates and pin-to-pin delay as fast as 4.5 ns.
MultiVoltTM I/O interface enabling MAX3000A series CPLDs’ device core to run at 3.3 V, while I/O pins are compatible with 5.0 V, 3.3 V, and 2.5 V logic levels. MAX3000A series CPLDs’ I/O is compatible with PCI and support programmable slew-rate control & Open-drain output option. Basic parameters of MAX3000A series CPLDs are shown in Table 1.
Table 1
MAX 3000A architecture consists of Logic Array Blocks (LABs), Macrocells, Expander product terms (shareable and parallel), Programmable Interconnect Array (PIA) and I/O control blocks. It also includes four dedicated inputs that can be used as general–purpose inputs or high–speed, global control signals (clock, clear, and two output enable signals).
The MAX 3000A device architecture is based on the links of high–performance LABs. LABs consist of 16–macrocell arrays. Multiple LABs are linked together via the PIA, a global bus that is fed by all dedicated input pins, I/O pins, and macrocells.
Macrocells consist of three functional blocks: logic array, product–term select matrix, and programmable register. Combined logic is implemented by the logic array, which provides five product terms per macrocell. The product–term select matrix allocates these product terms for use as either primary logic inputs (to the OR and XOR gates) to implement combined functions, or as secondary inputs to the macrocell’s register preset, clock, and clock enable control functions.
Two kinds of expander product terms are available to supplement macrocell logic resources. One of them is Shareable expander, which is the inverted product term as a feedback into the logic array. The other is Parallel expander, which is the product term borrowed from adjacent macrocells. The Altera development system automatically optimizes product–term allocation according to the logic requirements of the design.
For registered functions, each macrocell flipflop can be individually programmed to implement D, T, JK, or SR operation with programmable clock control. The flipflop can be bypassed for combined operation. MAX 3000A CPLD Block Diagram and MAX 3000A Macrocell are shown as below.
MAX 3000A CPLD Block Diagram
MAX 3000A Macrocell
Brief Introduction for MAX II Series
The MAX II family of instant-on, non-volatile CPLDs is based on a 0.18-μm, 6-layer-metal-flash process, with densities from 240 to 2,210 logic elements. MultiVoltTM I/O interface enables MAX II family CPLDs’ device core to run at either 3.3 V/2.5 V or 1.8 V, while I/O pins are compatible with 3.3 V, 2.5 V, 1.8 V, and 1.5 V logic levels.
MAX II devices contain a two-dimensional row- and column-based architecture to implement custom logic. Row and column interconnects provide signal interconnects between the logic array blocks (LABs).
MAX II devices provide a global clock network. The global clock network consists of four global clock lines that drive the entire device, providing clocks for all resources within the device. The global clock lines can also be used as control signals such as clear, preset, or output enable.
There are no FLIP-FLOPs in the IOEs, but there are Programmable Pull-Up, Optional PCI Clamp and bus-hold circuits in the I/O pins in the MAXII devices. There are drive strength control, slew–rate control and Open–drain output and other functions in the output drivers. Moreover, there is a single output enable signal (OE) responding to each output. There is Optional Schmitt Trigger Input which enhances anti-noise capability of the pins and increases the delay time by 300 ps approximately in the input drivers.
Global Clock Generation and IOE Structure are shown as below.
Global Clock Generation
MAX II IOE Structure
Brief Introduction for FPGA Products
Brief Introduction for Cyclone II Series Products
Altera Cyclone II FPGAs extend the low-cost FPGA density ranging from 4,608 to 68,416 LEs and provide up to 622 usable I/O pins and up to 1.1 Mbits of embedded memory. Cyclone II FPGAs are manufactured on 300-mm wafers using TSMC's 90-nm low-k dielectric process to ensure rapid availability and low cost. The low cost and optimized feature set of Cyclone II FPGAs make them the ideal solutions for a wide array of automotive, consumer, communication, video processing, test and measurement, and other end-market solutions.
Cyclone II devices support the Nios II embedded processor, which allows you to implement custom-fit embedded processing solutions. Cyclone II devices can also expand the peripheral set, memory, I/O, or performance of embedded processors. Cyclone II FPGAs can be used alone or used as DSP co-processors to improve price-to-performance ratios for digital signal processing (DSP) applications.
Cyclone II devices offer High-speed differential I/O standard support, including LVDS, RSDS, mini-LVDS, LVPECL, differential HSTL, and differential SSTL. Cyclone II CPLDs also support Single-ended I/O standard, including 2.5 V and 1.8 V, SSTL class I and II, 1.8 V and 1.5 V HSTL class I and II, 3.3 V PCI and PCI-X 1.0, 3.3, 2.5, 1.8, and 1.5 V LVCMOS, and 3.3, 2.5, and 1.8 V LVTTL. Cyclone II is compatible with 133-MHz PCI-X 1.0 specification and supports PCI Express with an external TI PHY and an Altera PCI Express×1 Megacore function.
There is a flexible clock management circuitry in Cyclone II devices, including Hierarchical clock network with up to 402.5-MHz performance, Up to four PLLs per device provide clock multiplication and division, phase shifting, programmable duty cycle, and external clock outputs, allowing system-level clock management and skew control. Up to 16 global clock lines in the global clock network drive the entire device.
Cyclone II devices have the embedded multiplier blocks optimized for multiplier-intensive Digital Signal Processing (DSP) functions, such as Finite Impulse Response (FIR) filters, Fast Fourier Transform (FFT) functions, and Discrete Cosine Transform (DCT) functions. Embedded multipliers can operate at up to 250 MHz (for the fastest speed grade) for 18 × 18 and 9 × 9 multiplications when using both input and output registers. Clock Control Block Locations and Multiplier Block Architecture are shown as below.
Clock Control Block Locations
Multiplier Block Architecture
Brief Introduction for Cyclone III Series Products
Cyclone® III device family is a cost-optimized, memory-rich FPGA family. Cyclone III FPGAs are built on TSMC's 65-nm low-power (LP) process technology with additional silicon optimizations and software features to minimize power consumption. Cyclone III is high–density PLDs with 5,136 to 119,088 LEs and provide up to 534 user I/O pins and up to 3.8 Mbits of embedded memory.
Cyclone III FPGAs’ device core operates at 1.2 V, while I/O pins are compatible with 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3 V and 3.3 V logic levels. Cyclone III FPGAs support Bus LVDS (BLVDS), LVDS, RSDS®, mini-LVDS and PPDS® differential I/O standards. The supported I/O standards include LVTTL, LVCMOS, SSTL, HSTL, PCI, PCI-X, LVPECL, LVDS, mini-LVDS, RSDS and PPDS; PCI Express and Serial Rapid I/O could be supported by using external PHY devices.
Cyclone III Device Architecture
Cyclone III External Memory Data Path
Cyclone III External Memory Interface
Cyclone III FPGAs offer support for high-speed external memory interfaces including DDR, DDR2, SDR SDRAM, and QDRII SRAM at up to 400 Mbps, Auto-calibrating physical layer (PHY) feature accelerates timing closure process and eliminates variations over process, voltage and temperature (PVT) for DDR, DDR2,SDRAM, and QDRII SRAM interfaces. EDEs can implement the controller function by using Altera DDR2/DDR SDRAM or QDRII SRAM memory controllers, third-party controllers, or a custom controller for unique application needs. Cyclone III devices use data (DQ), data strobe (DQS), clock, command, and address pins to interface with external memory. Some memory interfaces use the data mask (DM) or byte write select (BWS#) pins to enable data masking.
Cyclone III FPGAs are made up of M9K Embedded Memory Blocks, User I/O with Integrated OCT, Staggered I/O Ring, Embedded Multipliers for High-Throughput DSP, Les, 200 MHz Memory Interfaces and Dynamically Configurable PLLs. The Logic Array Block (LAB) consists of 16 logic elements (LEs) and a LAB-wide control block. Each LE has four inputs, a 4-input look-up-table (LUT), a register, and output logic. In the Cyclone III device architecture, interconnections between LEs, LABs, M9K memory blocks, embedded multipliers, and device I/O pins are provided by the MultiTrack interconnect structure which is a fabric of routing wires. The MultiTrack interconnect structure consists of performance-optimized routing lines of different speed that is used for inter- and intra-design block connectivity. The Quartus II software automatically optimizes designs by placing the critical path on the fastest interconnects.
Brief Introduce for Stratix II Series Products
The Stratix® II FPGA family is the high-end products of Altera and can be divided into the Stratix II family and the Stratix II GX family. Stratix II FPGA is based on a 1.2 V, 90-nm, all-layer copper SRAM process and features a new logic structure that maximizes performance, and enables device densities ranging from 15,600 to 179,400 equivalent LEs. Stratix II GX device densities can range from 33,880 to 132,540 equivalent LEs. Stratix II devices support various I/O standards along with support for 1 Gbps source synchronous signaling with DPA circuitry. Stratix II devices offer a complete clock management solution with internal clock frequency of up to 550 MHz and up to 12 phase-locked loops (PLLs). Stratix II GX devices include 4 to 20 high-speed transceiver channels, each incorporating clock and data recovery unit (CRU) technology and embedded SERDES capability with data rates of up to 6.375 Gbps. The transceivers are grouped into four-channel transceiver blocks, and are designed for low power consumption and small die size. Stratix II family also offer support for high-speed networking and communications bus standards including Parallel RapidIO, SPI-4 Phase 2 (POS-PHY Level 4), Hyper Transport™ technology, and SFI-4.
Stratix II and Stratix II GX device phase-locked loops (PLLs) provide robust clock management and synthesis for device clock management, external system clock management, and high-speed I/O interfaces. Stratix II devices have up to 12 PLLs, and Stratix II GX devices have up to 8 PLLs. Stratix II and Stratix II GX PLLs are highly versatile and can be used as a zero delay buffer, a jitter attenuator, low skew fan out buffer, or a frequency synthesizer.
Stratix II and Stratix II GX devices feature both enhanced PLLs and fast PLLs. Stratix II and Stratix II GX devices have up to four enhanced PLLs respectively. Stratix II GX devices have up to four fast PLLs, while Stratix II devices have up to eight. Both enhanced and fast PLLs are feature-rich, supporting advanced capabilities such as clock switchover, reconfigurable phase shift, PLL reconfiguration, and reconfigurable bandwidth. PLLs can be used for general-purpose clock management, supporting multiplication, phase shifting, and programmable duty cycle. In addition, enhanced PLLs support external clock feedback mode, spread-spectrum clocking, and counter cascading. Fast PLLs offer high speed outputs to manage the high-speed differential I/O interfaces. EDEs would find that they can use EPLLs merely and that FPLLs can not be used when they use DDR/DDR2 controllers which are designed by Altera or by themselves.
Stratix II and Stratix II GX Enhanced PLL
Stratix II and Stratix II GX Fast PLL
Stratix II GX devices integrate highly advanced 6.375 Gbps four-channel gigabit transceiver blocks. The Stratix II GX transceiver offer higher data rate support and additional features that enable you to support a wide variety of standards and custom protocols. Each self-contained Stratix II GX gigabit transceiver block has a variety of embedded functions to implement commonly required tasks.
Stratix II GX transceivers are structured into duplex four-channel groups called transceiver blocks. EDEs can configure each channel within a transceiver block in either single-width or double-width mode. Single-width mode has an 8-bit/10-bit serializer/ deserializer (SERDES) data path through the transceiver and supports data rates from 600 Mbps to 3.125 Gbps. Double-width mode has a 16-bit/20-bit SERDES data path through the transceiver and supports data rates from 1 Gbps to 6.375 Gbps. All blocks in the transceiver can operate in double-width mode, except deskew first-in first-out (FIFO), which is available only in single-width mode.
Stratix II GX transceiver Archtecture
Brief Introduction for Stratix III Series Products
The Stratix III FPGA family can be divided into the Stratix III L family and the Stratix III E family. The Stratix III L family provides balanced logic, memory, and multiplier ratios for mainstream applications. The Stratix III E family is rich in memory and multiplier for data-centric applications. Based on a 1.1 V, 65-nm all-layer copper SRAM process, the Stratix III family is a programmable alternative to custom ASICs and programmable processors for high performance logic, digital signal processing (DSP), and embedded designs and architectures. Stratix III devices include optional configuration bit-stream security through volatile or non-volatile 256-bit Advanced Encryption Standard (AES) encryption. Where ultra-high reliability is required, Stratix III devices include automatic error detection circuitry to detect data corruption by soft errors in the configuration random-access memory (CRAM) and user memory cells.
Stratix III device densities can range from 48,000 to 338,000 equivalent LEs. They support up to 16 global clocks, 88 regional clocks, 116 peripheral clocks per device, and up to12 phase-locked loops (PLLs) per device that support PLL reconfiguration, clock switchover, programmable bandwidth, clock synthesis and dynamic phase shifting, offering support for high-speed external memory interfaces including DDR, DDR2, DDR3 SDRAM, RLDRAM II, QDR II and QDR II+ SRAM on up to 24 modular I/O banks.
The Logic Array Block (LAB) is composed of basic building blocks known as Adaptive Logic Modules (ALMs) that can be configured to implement logic, arithmetic, and register functions. Each LAB consists of ten ALMs, carry chains, shared arithmetic chains, LAB control signals, local interconnect, and register chain connection lines. ALMs are part of a unique, innovative logic structure that delivers faster performance, minimizes area, and reduces power consumption. ALMs expand the traditional 4-input look-up table architecture to 7 inputs, increasing performance by reducing LEs, logic levels, and associated routing. In addition, ALMs maximize DSP performance by dedicated functionality to efficiently implement adder trees and other complex arithmetic functions.
High-Level Block Diagram of the Stratix III ALM
Seven-Input Functions in Extended LUT Mode
Brief Introduction for Stratix IV Series Products
Stratix IV FPGAs deliver a breakthrough level of system bandwidth and power efficiency for high-end applications, allowing designers to innovate without compromise. Stratix IV FPGAs are based on TSMC’s 40-nm process technology and surpass all other high-end FPGAs available today with the highest logic density, most transceivers, and lowest power. The Stratix IV device family contains two variants optimized to meet different application needs, Stratix IV GX transceiver FPGAs - up to 531,200 logic elements (LEs) and 48 full-duplex clock data recovery (CDR)-based transceivers at up to 8.5 Gbps. Stratix IV E (Enhanced) FPGAs - up to 681,100 LEs, 31,491 Kbits RAM, 1,360 18×18-bit multipliers.
Stratix IV family has dedicated high-performance digital signal processing (DSP) blocks optimized for DSP applications. Stratix IV devices are ideally suitable for using as the DSP blocks that consist of a combination of dedicated elements that perform multiplication, addition, subtraction, accumulation, summation, and dynamic shift operations. Along with the high-performance Stratix IV soft logic fabric and TriMatrix™ memory structures, EDEs can configure these blocks to build sophisticated fixed-point and floating-point arithmetic functions. These can be manipulated easily to implement common larger computationally intensive subsystems such as finite impulse response (FIR) filters, complex FIR filters, infinite impulse response (IIR) filters, fast Fourier transform (FFT) and discrete cosine transform (DCT) functions. DSP blocks support 9-bit, 12-bit, 18-bit, 36-bit wordlengths, 18-bit complex multiplications, cascading 18-bit input bus to form tap-delay line for filtering applications and Cascading 44-bit output bus to propagate output results from one block to the next block without external logic support.
Half-DSP Block Architecture
Written By Arthur Zou
Sep. 19, 2008