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FPGA and CPLD Development Tools and Design Flow
Abstract
This article is the third section in the FPGA and CPLD Guide series and will introduce the common development tools and design flow of the PLD devices with focus on Altera.
Brief Introduction of FPGA and CPLD Design Flow
As described in the PLD Device Overview, the entire FPGA & CPLD design flow includes circuit design input, functional simulation, synthesis, post-synthesis simulation, implement, post-route simulation & verification, Board level simulation & validation & debugging, etc.
Circuit design input means inputting EDEs’ conception of circuit design to the EDA tools such as QuartusII by some canonical description methods so that EDEs can implement their design and debugging. Common methods for design input include HDL, Schematic, Wave and State Machine, etc. HDL and Schematic are used to implement the top level design and the bottom level design. Schematic is explicit and easy to understand. But in the case of large projects, it presents more disadvantages such as hard to maintain, rebuild and reuse design modules. The primary disadvantage is hard to simulate and debug. So, HDL is still the prevailing design input means up to the present.
Functional simulation is also called preliminary simulation, and its main target is to debug and verify logic function. The prevailing tool is ModelSim software at present. EDEs must write TestBench or input test wave to simulate an external platformform. The TestBench files need improving continuously in order to eliminate more omissions and design errors. Functional simulation is very fast and need only a few minutes or even seconds comparing with post simulation. Setting of test conditions in the TestBench files is the key to find problems in the design. If the result of Functional simulation and is close to that of the actual instance of the circuit, EDEs can reduce many workloads while they implement the post simulation and Board level simulation & verification & debugging, and they would find that there are a few differences between the corresponding processes of Functional simulation and the actual instance at that time.
Synthesis refers to translating and editing circuit design implemented with HDL or schematic, as well as optimizing it to create new logic connects, i.e., connecting or cutting those fuses between the Row lines and the column lines. The prevailing tool is Synplify / Synplify Pro software now. Some FPGA manufacturer such as Altera and Xilinx also offer their Synthesis tools which is embedded in the QuartusII or ISE.
Post-route simulation & verification is also called post simulation and its main target is to debug and verify timing logic function. The prevailing tool is ModelSim software at present. EDEs need to add timing restriction conditions and adjust it in the TestBench files. Post simulation is very slow and usually needs several hours or even days. It is very complicated to implement the Post simulation for Altera FPGA Products. Post simulation’s result is closest to that of the actual instance of the circuit but there are some differences between them.
HDL Language Overview
HDL means Hardware Description Language. HDL’s main function is compiling the design file and building the simulation model of behavior level for the electronic system. It is mainly used for digital system modeling of many abstract design levels from arithmetic level to gate level and finally to switch level. In the EDA field, the digital model built with HDL language is called Soft Core, and the netlist created after modeling with HDL and synthesis is called Hard Core. It would shorten development cycle, and improve design efficiency by reusing Soft Core and Hard Core.
HDL was put forward by Iverson Company firstly in 1962. There are many HDLs such as SFL, ISP, BLM emerging so far. The most excellent is VHDL and Verilog HDL.
VHDL is the prevailing HDL at present and had become IEEE STD_1076 standard. VHDL fits for the large design project and hardware description on system level. It supports Top Down and Library-Based design means. It is also supported by most of EDA development tools. VHDL is independent of the process and lay particular stress on the standardization. A complete VHDL program usually includes five sections such as Entity, Architecture, Configuration, Package and Library.
Verilog is the other popular HDL and had become IEEE STD_1364-1995 standard. Verilog HDL is based on C Language and fits for the small design project and IC/PCB level description. Verilog lays particular stress on the collaboration with EDA tools. Code style of Verilog is more concise and more efficient comparing with VHDL.
Overview of Common Development Tools
Overview of Quartus II
The Altera Quartus II design software provides a complete, multi-platform design environment that easily satisfies your specific requirements. It is a comprehensive environment for SOPC design. The Quartus II includes solutions and third software interface for all the phases of FPGA and CPLD design. Designers can use Synplify / Synplify Pro software for synthesis and ModelSim software for simulation.
EDEs can use SignalTapII and SignalProbe for analyzing logic design waveform in internal nodes and I/O pins of devices, use Timing Analyzer for orientating, analyzing and improving critical path and advance operation frequency in design, use Chip Editor, Floorplan Editor, Design Space Explorer and PowerFit Fitter for observing, planning, analyzing and modifying Fitter instance inside the device, use PowerGauge for evaluating device’s power.
ModelSim Overview
ModelSim is a special simulator which is the most popular simulation tool at present. Designers need to write TestBench files and design the outside simulation platformform, Test Vector, timing information, launching condition and operation process to simulate the outside simulation platform and set DUT. To accomplish a perfect simulation, designers also can write real-time comparison and check conditions in TestBench files. The main design requirement of TestBench and Test Vectors is covering all of aspects and all the corners about DUT as many as possible.
Generally speaking, Behavior Level description should be used in the TestBench files but RTL Level description should not be used. Users can use ModelSim-Altera edition, otherwise they have to compile Altera component Library files. Some commands under the command line mode used in ModelSim should be not forgotten; they are vcom, vsim and run. The commands are shown as below.
Vcom –work <library_name> <file>.vhd <file2>.vhd
Vsim [options] [[<library>.]<top_level_design_unit>[(<secondary>)]]
RUN [<timesteps>[<time_units>]]|[-all]|[-continue]|[-finish]|[-next]|[-step]|[-over]
Vcom command is used to compile VHDL source file in design and test bench file, vsim command is used to load Top level design unit and launch the simulation, RUN command is used to implement simulation.
Configuration and Design security
Based on the function of FPGA in the configuration circuit, configuration data is downloaded to the target device in three modes; they are FPGA Active mode, FPGA passive mode and JTAG mode. Under FPGA Active mode, the target FPGA actively outputs control signals and synchronization signals (include the configuration clock) to the dedicated serial configuration chip of Altera. As long as the commands are received, the configuration chip would send the configured data to the target FPGA and finish configuration. Under FPGA passive mode, other devices in the system launch and control the configuration process, FPGA is completely in a passive position and it merely output some status signals to cooperate in configuration process. FPGA passive mode can be divided into many types including PS (Passive Serial), FPP (Fast Passive Parallel), PPS (Passive Parallel Synchronous), PPA (Passive Parallel Asynchronous) and PSA (Passive Serial Synchronous).
Configuration data is stored in SRAM cells when FPGA is working normally. After FPGA is powered on, the external circuit reloads configured data to the On-Chip configuration RAM. Then, internal registers and I/O pins must be initialized. Finally, FPGA enter the User-Mode. Under the Configuration mode and Initialization mode, user I/O is under the state of high impedance or internal weak pull-up. Under the User-Mode, user I/O works as the functions designed by users. The entire configuration process has three stages which include Reset, Configuration and Initialization. Configuration process is shown as below.
Configuration Cycle Waveform
Some high-end FPGA as StratixII, StratixIII and StratixIV devices support configuration data decompression, which saves configuration memory space and time. This feature allows EDEs to store compressed configuration data in configuration devices or other memories, and transmit the compressed bit stream to high-end FPGA devices. During configuration, the high-end FPGA decompresses the bit stream in real time and programs its SRAM cells. Preliminary data indicates that compression typically reduces configuration bit stream size by 35 to 55%. High-end FPGA supports decompression in the FPP (when using a MAX II device/microprocessor + flash), AS, and PS configuration schemes. Decompression is not supported in the PPA configuration scheme. Neither is in JTAG-based configuration.
These high-end FPGA as StratixII, StratixIII and StratixIV are the first industrial devices with the ability to decrypt a configuration bit stream using the Advanced Encryption Standard (AES) algorithm—the most advanced encryption algorithm available today. When using the design security feature, a 128-bit security key is stored in the FPGA. In order to successfully configure a FPGA which has the design security feature enabled, it must be configured with a configuration file that was encrypted using the same 128-bit security key. The security key can be stored in non-volatile memory inside the FPGA. This non-volatile memory does not require any external devices, for example a battery back-up, for storage.
Embedded System Design Based on Nios II Processor
System-on-a-programmable-chip (SOPC) is a flexible and effective SOC solution put forward by FPGA manufacturers. SOPC integrates Hard-Core CPU or Soft-Core CPU, DSP, Memory, I/O peripheral and PLD in a single chip. This is a subminiature embedded system implemented by a single chip! SOPC is designed based on the Nios II processor of Altera.
Nios II Processor Core Block Diagram
Example of a Nios II Processor System
The NiosII processor is a general-purpose RISC processor core with 200 DMIPS. NiosII processor supports full 32-bit instruction set, data path, and address space. The Nios II architecture supports separate instruction and data buses, and is classified as Harvard architecture. Both the instructions and data buses are implemented as Avalon™ master ports that adhere to the Avalon interface specification. The data master port is connected to both memory and peripheral components, while the instruction master port is connected only to memory components.
Currently, Altera offers three Nios II cores. The fastest one is Nios II/f core which is designed for high performance. As a result, this core presents the most configuration options allowing EDEs to fine-tune the processor for performance. The standard one is Nios II/s core which is designed for small size while maintaining the performance. The economic one is Nios II/e core which is designed to achieve the possible smallest core size. As a result, this core has a limited feature set, and many settings are not available when the Nios II/e core is selected. Altera allow users to customize NIOSII processor and select appropriate Memory, peripheral and I/O interface based on their requirements. EDEs can also integrate special functions as DSP and User Logic.
Written By Arthur Zou
Sep.28,2008