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Common Programmable Logic Design Techniques
ABSTRACT
This article is the fourth section in the FPGA and CPLD Guide series and will introduce Common programmable logic design techniques with emphasis on Basic design rules for programmable logic, Common design thought and technique and Coding style recommended by Altera.
Basic Design Rules for Programmable Logic
There are some basic design rules for programmable logic including principle of Balance and Interchange between area and speed, Hardware principle, System principle and Synchronous principle.
Principle of Balance and Interchange between Area and Speed
Area refers to logic resource quantity used in FPGA/CPLD in a design project. It can be scaled with FF and LUT which is used for FPGA, and with MC which is used for CPLD. Speed refers to the maximal frequency that could be obtained while a circuit operates stably in a chip. It is determined by the timing status of the design and has close relations with Clock Cycle, PAD to PAD Time, Clock Setup Time, Clock Hold Time, Clock-to-Output Delay and other characteristic values of timing which must meet the requirement of design. Area and Speed are the ultimate standard to evaluate design quality.
The scientific design target requires that a design should satisfy the design timing requirement with least area taken in chip, or a design should get the better timing slack and higher frequency within the prescribed area. Speed should be prior to Area while they collide with each other.
Hardware principle
EDEs should understand the principle of programmable logic design. Essentially, programmable logic design is a large-scale digital integrated circuit design and debugged by software means. So, EDEs must think it as hardware, and then take the circuit solution into consideration efficiently and reasonably from the point of view of hardware.
System principle
EDEs should think about Design Partitioning and Assignment from the point of view of system and make reasonable arrangement for the design, such as clock domain, module reuse, timing restriction, Area and Speed, etc. Commonly, FPGA fits for those designs which are of larger scale, higher frequency and rich register resource.
Synchronous principle
There are some differences between synchronous circuit and asynchronous circuit. Firstly, the Core logic of asynchronous circuit is implemented with combination circuit, and the Core logic of synchronous circuit is implemented with all kinds of FFs. Secondly, the main signals, output signals and other signals of asynchronous circuit is independent of any clock signal and, the main signals, the output signals and other signals of synchronous circuit are produced by certain clock edge drive FFs. Thirdly, the fatal flaw of asynchronous circuit is that it is easy to produce glitch, but it is on the contrary for synchronous circuit. Finally, asynchronous circuit is not suitable for component transplant, STA and verification for designed sequential logic performance, but it is the opposite for synchronous circuit.
Timing validity of asynchronous logic design depends on the delay of every logic component and routing completely. So, its timing restriction is relatively complex and hard and liable to produce glitch, metastability and other problems, resulting in low frequency and drop-in design stability.
Basic rule of synchronous design is launching all the operations with the same kind of clock edge. In the synchronous design, stable data sample must be based on two basic principles. One of them is fulfilling Setup time principle which refers to that the input data has been held in stable status for at least Setup time of sample register before the effective clock edge arrived. The other is fulfilling Hold time principle which refers to that the input data would be held in stable status for at least Hold time of sample register after the effective clock edge arrived. The common design method for circuit delay in the synchronous design is to achieve the needed delay by using synchronous counter, frequency division clock or frequency multiplication clock.
Common Design Thought and Technique
There are some Common design thoughts and techniques for programmable logic which include ping-pong operation, series-parallel translation, pipelining operation and data interface synchronous.
Ping-pong Operation
Ping-pong operation is a common design technique used to control data stream. You can understand the operation process through viewing the figure “Ping-pong Operation”. Input data stream is divided into the odd frame and the even frame by the Input data stream selection unit. Then the odd frame and the even frame go into the corresponding data operation channel respectively. The output data stream selection unit selects one from the two data channel and sends it to the next approach at a time. The input data stream goes into channel 1, while data in channel 2 is sent to the output data stream selection unit. The principle is shown as below.
Ping-pong operation implements the operation for high-speed data stream with low-speed operation modules, saving the data buffer space. Its essential is Series-parallel translation of data stream implemented with DPRAM.
Series-parallel Translation
Series-parallel translation is also a common design technique used to control data stream. Its target is to increase data transfer speed in the whole design by copy logic. Its essential is to increase system work speed by expending more logic resource.
Pipelining Operation
Pipelining operation is a common design technique in the high-speed design field. If the operation process in a project could be divided into some steps and the entire data operation process is in a single direction which means no feedback operation in the process. The output of every step is the input of the next step. EDEs can increase design frequency of system by using Pipelining operation. Pipelining design architecture is shown as below. The key of Pipelining design is to arrange the entire design scheduling in reason and match the data stream speed between the previous step and the next step.
Data Interface Synchronization
Data Interface Synchronization refers to exchanging data reliably in two asynchronous clock domains. Data interface Synchronous includes two instances; one is the problem of variable phase with same frequency which means same clock frequency with unfixed phase difference or fixed and unknown phase difference between two clock domains. The other is different clock frequency between two clock domains which is called different frequency problem.
There are two methods for asynchronous clock domain translation which are not recommended for the FPGA/CPLD design. One is sample time adjustment with buffer and other combination logic delay line, the other is sample time adjustment with negative clock edge and positive clock edge at the same time.
There are many drawbacks of the delay produced with combination logic such as easy to produce glitch, bad timing margin, hard to transplant, worse maintainability. If EDEs operate with negative clock edge and positive clock edge at the same time, they would find that the effect corresponds to that of a frequency multiplication clock with same phase. All of interrelated using constraints would become more compact and be hard to implement reliably. Most of PLLs and DLLs can better control the Jitter, Skew and other parameters for single clock edge, but is unsuitable for two clock edge during the same clock cycle.
A simple solution for the problem of variable phase with same frequency is sampling the front end data twice with the back end clock. It can reduce propagation of the metastability and fits for the function units that is insensitive to a few mistakes. The reliable solution for the problem of variable phase with same frequency and the problem of different frequency is exchanging data in asynchronous clock domains with a kind of data buffer which is possibly DPRAM, FIFO or a segment register buffer. EDEs need to write the front end data into the data buffer with the upper associated clock, and read data with the corresponding clock.
Metastability
The sticking point for data exchange in asynchronous clock domains is to ensure the proper Setup time and Hold time when the front-end data is sampled with the back-end clock. If the Setup time and Hold time were not met, the metastability would be possibly produced. As a result, the output of FFs is uncertain. The metastability would destroy the stability of system and lead to mistakes of logic judgment. EDEs must implement sampling with three level registers and synchronous design.
Coding Style Recommended by Altera
FPGA engineers need to notice something about coding style when they write and debug FPGA programs, which include Hierarchical Coding, Design Partitioning, Sense Signal Table and FSM, etc.
Hierarchical Coding
The Hierarchies should be 3 to 5 levels. It is the best that the top module merely includes organizing and calling for all the modules. The interfaces are allowed to exist among the sub-modules, but inter-hierarchical interfaces are not recommended. Module partitioning is very important and should be considered in many aspects such as function, architecture, timing and complication, etc.
Design Partitioning
There are basic rules for Design Partitioning should be noticed. EDEs should partition every synchronous timing design module with register, put all the interrelated or reusable logics in the same module, detach different logics which have different optimization target, arrange all relaxant logics in the same module, group the memory logics into a single module, every module should have appropriate scale. EDEs should also avoid using Combinational Loops and Asynchronous Delay Chains.
Signal Sensitivity List
The design method of correct signal sensitivity list is listing all the input signals and conditional judgment signals used in the process in the signal sensitivity list. Incomplete signal sensitivity list can lead to the disagreement between the results of functional simulation and post simulation.
FSM
Finite state machine is a kind of design input method and is also a kind of design technique. FSM is the general model for the sequential circuit. It is made up of registers and combinational logic in substance. The elements that compose FSM include the input (including Reset), State (including operations for the current state), State transfer condition and output condition. The transfer among various states is always launched by the clock.
FSM could be divided into Mealy mode and Moore mode. For Moore mode, the next state is merely determined by the current state. For Mealy mode, the next state is determined by the current state and the current input value.
EDEs should write the State transfer in a single module and write operations for the current state and output condition of state in the other module. They should use Gray-code and binary code for the small design and use one-hot code for the large design. A complete FSM should include initialization state and default state. EDEs should appoint a default output value for all the output variables.
Written By Arthur Zou
Oct.08, 2008