| Contents | Part 1 | Part 2 | Part 3 | Part 4 | Part 5 | Part 6 | Part 7 | Part 8 |
FPGA Timing Demand
ABSTRACT
This article is the fifth section in the FPGA and CPLD Guide series and will introduce FPGA Timing demand with emphasis on Clock Skew, Clock Jitter and Timing Margin.
Clock Skew and Clock Jitter
The Clock Skew refers to the clock phase reach to various clock terminals in the same clock partition system is inconsistent. The Clock Skew is mainly caused by two factors, one is the differences among clock sources, and the other is the skew of the clock partition network. The Clock Skew always exists and badly affects the timing of designs.
Clock Skew
Clock Jitter
The Clock Jitter refers to differences between actual output position and the ideal output position of the clock edge. The Clock Jitter can be divided into the fixed Jitter and the random Jitter, the fixed Jitter has more timing offset and can trace to the specific source such as signal noise, crosstalk, power system, etc. The random Jitter is derived from environmental factors such as heat interference, the radiation, etc.
Timing Margin
The timing is the determining factor in a synchronization circuit. In order to make sure a synchronization circuit can operate as usual, all of timing routing delay must less than the clock cycle set by the system in the synchronization circuit. If the delay of certain routing went beyond the timing limit, the whole system will function abnormally. Moreover, for the high-speed system design, how to meet the timing demand of the design while making sure the correct design functions is a huge challenge for designers. So, designers need to think about various possible factors and calculating accurately the timing margin in order to make sure the system reliability.
Synchronization design timing model diagram
While calculating accurately the timing margin inside the design, engineers need to think about some delay factors that include MicroTco, the delay from the clock to the output of the source FF; Tlogic, the routing and logic delay from a FF to the other FF; MicroTsu, the setup time of the destination FF; and MicroTh, the hold time of the destination FF. On the assumption that the clock cycle determined by the design specification is T，then the demand that meets the setup time of the clock is shown as the formula:
MicroTco + Tlogic + MicroTsu ≤ T………………………………………… (Formula 1)
Meanwhile, the design also needs to meet the demand of MicroTh
For the synchronization interface design, the other critical point is the interface timing between FPGA and the circumjacent devices. Because there are a longer delay exists in the input and the output of chip’s I/O Pins, as well as the phase relations with the clock signals, the timing of the interface circuit become the difficulty in design.
While calculating accurately the timing margin of I/O Pins, EDEs need to think about some delay factors, including Tco, the clock-to-output delay of the source device; Tfight, the PCB routing delay; Tsu, the setup time of the destination device; and Th, the hold time of the destination device. On the assumption that the clock cycle decided by the design specification is T, then the demand is shown as the formula:
Tco + Tfight + Tsu ≤ T………….………………………………………………... (Formula 2)
At the same time, the design also needs to meet demand of Th
These calculations is based on a basic springboard, the clock inside FPGA and the system clock on PCB are perfect clock. In other words, the clock possess constant clock cycle and without Jitter. However, that kind of clock is inexistent in the actual system.
In the past, engineers usually only considered logic levels, area layout and routing delay as the most important timing problems in the design. They seldom consider the characteristics of the clock, such as the Skew, Jitter, Duty Cycle Distortion, etc. For the low-speed designs, it is unnecessary on the whole to take them into consideration for engineers. However, with the continuous increase of the design clock frequency, the drawback of clock is turning out the constant reduction of the valuable timing margin and design performance. Therefore, designers had to attach more importance to the clock quality.
If the delay to the source FF is less than the delay to the destination FF, Tskew is positive value, otherwise negative value. If the actual clock cycle less than the ideal clock cycle, Tjitter is positive value, otherwise negative value. If the next effective clock edge arrived ahead of the scheduled time, effective clock cycle would be shorter. Meanwhile, in order to meet the need of circuit for operating normally in the same clock cycle, designers need to think about the clock Skew and the clock Jitter, the demand is shown as the formula:
MicroTco + Tlogic + MicroTsu ≤ T + Tskew – Tjitter……………………………………… (Formula 3)
Similarly, the clock Skew and the clock Jitter in PCB also have to be considered.
Written By Arthur Zou
Oct.08, 2008