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Circuit Design Guide of FPGA System
ABSTRACT
This article is the sixth section in the FPGA and CPLD Guide series and will introduce the Circuit Design of FPGA System with an example in brief.
In a common embedded system, FPGA works as a processor which carries out certain operation or certain digital signal processing. Because FPGA is a large scale digital integrated circuit in essence, the central controller is generally a MCU or NiosII soft-core or a Powerpc Hard-core. Commonly a whole embedded system consists of MCU, FPGA, power supply circuit, external memory, sensor and other functional units. Next, let us discuss the system peripheral circuit design based on an example.
DDR Tester Whole Frame Diagram
The figure shown above is a whole frame diagram of DDR tester. The DDR tester is made up of LCD controlling Board& LCD, Main Board, Power supply Board and interface Board. The Main Board is the principal part of this tester. The MCU has the topmost controlling privilege and control everything of this system. FPGA is the core of this system and responsible for testing DDR chips under the control of the MCU and returning the feedback of test result to the MCU. LCD is the display terminal. LCD and the keyboard act as the interface between the tester and the user.
System Circuit Diagram
The figure shown above is the explicit and complete system circuit diagram. The MCU LPC2214FBD144/01,5 has the topmost controlling privilege and is based on the ARM-7 embedded core. LPC2214FBD144/01,5 sends commands and parameters to FPGA and then receives the status information and the test result from FPGA. Users can communicate with LPC2214FBD144/01,5 via the LCD and the keyboard. LPC2214FBD144/01,5 also tests the temperature of FPGA via MAX1619 and adjusts the Fan speed simultaneously. LPC2214FBD144/01,5 can control MAX8505, MAX4173, MAX1364 and DS3902 to adjust DDR test voltage and monitor the current. LPC2214FBD144/01,5 can also interface with RS232 bus and generic USB1.1 via CH375 and SP3232E.
LPC2214FBD144/01,5 is a 16-bit/32-bit ARM7TDMI-S microcontroller in 144 pin package, manufactured by NXP with 16 kB of on-chip SRAM and 256 kB of on-chip flash program memory. The operating voltage of CPU is 1.8 V ± 0.15V, and I/O power supply voltage is 3.3 V ± 10 %.
EP2S15 is the core of the DDR tester. It belongs to Stratix II family of FPGA of Altera. Based on the instructions of LPC2214FBD144/01,5, EP2S15 sends commands to DDR chip and set status registers for it, writes specific data and reads them out from DDR. Eventually, EP2S15 returns the test result to MCU. EP2S15 is based on a 1.2-V, 90-nm, all-layer copper SRAM process, possess 15,600 equivalent Les,12 DSP blocks, 48 18-bit × 18-bit multipliers, 2 EPLLs, 4 FPLLs and 419,328 bits RAM. FPGA program data is stored in Flash and loaded to EP2S15 via EPM3256A which belongs to MAX3000EEUP Family of CPLD of Altera.
IDT5V9885 is a programmable clock generator designed for high performance data-communications, telecommunications, consumer, and networking applications. The IDT5V9885 can be programmed through the I2C or JTAG interfaces. The main clock in this tester is variable based on MCU instructions, which is the output of IDT5V9885.
MAX1619 is a Remote/Local Temperature Sensor with Dual-Alarm Outputs and SMBus Serial Interface.
The remote sensor is a diode-connected transistor - typically a low-cost, easily mounted 2N3904 NPN type - that replaces conventional thermistors or thermocouples. No Calibration Required, MAX1619 also supports Programmable Under/Overtemperature Alarms and fan control. The MAX1619 is designed to work in conjunction with an external microcontroller (μC); the μC is typically a power management or keyboard controller. Temperature data will be automatically compared with the data previously stored in the four temperature-alarm threshold registers. One pair of alarm-threshold registers is used to provide fan control; the other pair is used for alarm interrupt.
The main chip of the power supply circuit in the system is MAX8543 manufactured by Maxim. The +12V input voltage is transformed into +5V, +3.3V, +2.5V, +1.8V and +1.2V to supply all other functional circuits. One of +2.5V is transformed into +1.25V SSTL2 voltage by LP2995M as the power supply for DDR terminal. One of +5V is supplied to MAX8505, MAX4173, MAX1364 and DS3902 to adjust DDR test voltage and watch the current.
MAX8543 is a current-mode, constant-frequency PWM buck controller operating from 3V to 13.2V input voltage and generating adjustable 0.8V to 0.9x VIN output voltages at loads up to 25A. The MAX4173 is a low-cost, precise, high-side current sense amplifier. The MAX8505 is a step-down regulator operating from a 2.6V to 5.5V input and generating an adjustable output voltage from 0.8V to 0.85 ✕ VIN at up to 3A. The MAX1363/MAX1364 is a low-power, 12-bit, 4-channel analog-to-digital converter (ADCs), which features a digitally programmable window comparator with an interrupt output for automatic system-monitoring applications. The DS3902 is a dual-port, nonvolatile (NV), low temperature-coefficient, variable digital resistor with 256 user-selectable positions.
Written By Arthur Zou
Oct.17,2008