GN4121 or GN4124 are single lane and 4-lane PCIe to local bus bridges:
- GN4121 is a single lane PCIe ver1.1 interface at 2.5Gbps.
- GN4124 is a 4-lane PCIe ver1.1 interface at 2.5Gbps or 10Gbps in each direction.
- Integrated PHY, transaction, and link layer.
- Two hardware virtual channels to enhance quality of service (QoS) - GN4124. One hardware virtual channel for GN4121.
- Payload size of up to 512 bytes with up to 4 outstanding transactions in each direction.
- Supports 3 x 64-bit Base Address Registers.
- Uses SSTL dual data rate I/O for high-speed data transfer (16 lanes and 800MBps in each direction) to FPGA.
- Local bus may be operated asynchronously to the PCIe clock rate for power optimization.
- “Live” on power up so a plug and play BIOS can auto-detect without FPGA activity.
- I2C master/target.
- 256 pin (17 x 17mm) BGA package.
- Typical power consumption for GN4124 is <950mW.
- Typical power consumption for GN4121 is 750mW.
- 0 to +85 deg.C temperature range.
- Royalty free local bus FPGA IP.
GN4124 & GN4121 Key Value Added Advantages
- Typically achieve 3x to 6x the performance of 64-bit legacy PCI solutions.
- An inexpensive way to add PCIe interface(s) to almost any low to mid range Altera Cyclone-III and Xilinx Spartan-6-LX FPGAs.
- Expensive Virtex-6-LXT, Spartan-6-LXT and Stratix-II-GX, Stratix-IV-GX, Arria-II-GX FPGAs with integrated transceivers offering end-point PCIe functionality can be offset by the GN4124 if more than one PCIe lane is required. Design engineers can adopt a smaller FPGA derivative at lower cost and lower power consumption.
- Avoid the need to pay for IP licensing and the cost of FPGA engineering resources to make it work - i.e., the time taken to sort out all the FPGA timing issues and application layer s/w integration etc.
- Unique “on-the-fly” ability to download firmware (software driver upgrades) directly to the FPGA over the PCIe link thus eliminating a separate FPGA configuration memory chip.
- Can boot up without FPGA involvement meaning true live activity at power-up eliminating any concerns over the host not being ready because it is still downloading a bitstream from external memory.
- On system power-up, both bridges respond to configuration cycles without the FPGA being active so the BIOS or operating system will never access the FPGA before it has been properly configured. i.e., this is known as enumeration and if it does not work it can cause system failures and cost in equipment downtime/debug/fixing.
- Offers additional GPIO to the FPGA - good for tweaking system settings, programming external CPLDs.
- In video applications, the Gennum PCIe bridges are capable of simultaneous HD video capture (1080p) and playback which legacy PCI solutions cannot match.