CDCLVP1204 Four LVPECL Output Clock Buffer
General Description:
The CDCLVP1204 is a highly versatile, low additive jitter buffer that can generate four copies of LVPECL clock outputs from one of two selectable LVPECL, LVDS, or LVCMOS inputs for a variety of communication applications. It has a maximum clock frequency up to 2 GHz. The CDCLVP1204 features an on-chip multiplexer (MUX) for selecting one of two inputs that can be easily configured solely through a control pin. The overall additive jitter performance is less than 0.1 ps, RMS from 10 kHz to 20 MHz, and overall output skew is as low as 15 ps, making the device a perfect choice for use in demanding applications.
The CDCLVP1204 clock buffer distributes one of two selectable clock inputs (IN0, IN1) to four pairs of differential LVPECL clock outputs (OUT0, OUT3) with minimum skew for clock distribution.
Features:
- 2:4 Differential Buffer
- Selectable Clock Inputs Through Control Pin
- Universal Inputs Accept LVPECL, LVDS, and LVCMOS/LVTTL
- Four LVPECL Outputs
- Maximum Clock Frequency: 2 GHz
- Maximum Core Current Consumption: 45 mA
- Very Low Additive Jitter: <100 fs,rms in 10-kHz to 20-MHz Offset Range
- 2.375-V to 3.6-V Device Power Supply
- Maximum Propagation Delay: 450 ps
- Maximum Output Skew: 15 ps
- LVPECL Reference Voltage, VAC_REF, Available for Capacitive-Coupled Inputs
- Industrial Temperature Range: –40°C to +85°C
- ESD Protection Exceeds 2 kV (HBM)
- Available in 3-mm × 3-mm QFN-16 (RGT) Package
Applications:
- Wireless Communications
- Telecommunications/Networking
- Medical Imaging
- Test and Measurement Equipment
Related Product Information:
Part No | Description |
CDCLVP1204RGTT | Four LVPECL Output Clock Buffer |
CDCLVP1216RGZT | LOW JITTER, 16O/P, LVPECL BUFFER |