P2020 Development System

  • P2020E QorIQ™ multicore communications processor, built on Power Architecture technology
  • Memory
    • 2 GB DDR3 DIMM
    • 128 MB NOR flash memory
    • 16 MB SPI ROM
    • 256B NVRAM
  • PCI Express: dual x2 slot
  • Ethernet
    • eTSEC1: RGMII
    • eTSEC2: RGMII or SGMII
    • eTSEC3: RGMII or SGMII
  • IEEE® 1588
    • Clock input from precision oscillator
    • Accessible via test header
  • Dual I2C
  • SD/MMC card slot
  • USB Type A connector
  • UARTs: Two DB9 connectors
  • SATA2
  • GPIO: 16
  • Three 10/100/1000 Ethernet connectors
  • SGMII riser card slot
  • System logic (Pixis FPGA)
    • Manages system reset sequencing
    • Manages system bus and PCI clock speed selections
    • Implements registers for system control and monitoring
  • System clock
    • SYSCLK switch can be set to one of eight common settings in the interval 33 MHz–166 MHz
  • DDR clock
    • DDRCLK switch can be set to one of eight common settings in the interval 33 MHz–166 MHz
  • Power supplies
    • Combined regulator for VDD and VDD_PLAT (nominally 1.05V)