Have a question about ADCs or DACs? Ask our Expert, Nick Gray

Nicholas,

Thank you for the advice. I am going to contact Picotech and see if they can correct the bugs.

As for programming, I could do it, but I want to finish this project and get it to market quickly. Writing a GUI and backend would take longer than I want to spend. If you could connect me with your friend in California, I would greatly appreciate it.

Cabe

Hello Nick,

I have to monitor voltage of each battery in the battery stack of 150 lead acid batteries. Each battery have voltage range from 1.5V to 3V. Can you suggest me the best method.

Balakrishna Nuthakki.

I am sorry that Picotech will not support their software. Unfortunately, I know of no one who is doing something similar. Hopefully, you and Rob can work something out. I sent him your email address. He is quite busy, but might be able to help you if the task is not too large.

- Nick Gray

I am sorry that I somehow missed your question.

Yes, some manufacturers of FPGAs are attempting to implement ADCs in their FPGAs. My personal feeling is that this will be a little difficult for them to do because the digital noise generated by the gates will cause the die substrate (on-chip common) to be quite noisy, which will add noise to the ADC conversion. Noise will most probably also find its way into the ADC reference voltage, further exacerbating the noise problaem. There are ways to get around this, however, but the result in any case is a relatively low conversion rate. Cost wise it should be beneficial to the end user, especially since more than one company is doing this and competition should keep the cost down. Performance is another story. If the ADCs are 8 or perhaps 10 bit resolution, there should be little problem with reasonable performance, although a stand-alone ADC should perform better than an imbedded one. At resolutions of 12 bits and more, I believe that performance will be no better than perhaps 10 bits.

What this means is, basically, that only the most significant 8 to 10 bits will be reliable, with the rest being mostly noise. The way around this would be to average many samples, but I doubt that this will increase performance beyond the 12 bit level, or 14 bit level at the most. And this would be satisfactory for most applications. Another approach would be to use converter topology that is relatively immune to noise, like a multi-slope ADC.

The problem I see is that there may not be provision to adjust for the offset and gain error of the ADC and the manufacturers will have the task of being sure that the user knows how to do this to prevent a lot of complaints and disgruntled users. These companies are digital and may not appreciate the analog problems unless they hire the right analog engineers. Some of the offset and gain errors can be done with conditioning circuitry before the ADC input of the FPGA, but these errors can vary from one individual part to another, so could probably more effectively be handled in the system processor.

As for applications where this might be beneficial, any system that takes input from the outside world and needs the versatility of an FPGA could potentially benefit.

- Nick

Hello, Balakrishna -

I have studied the LTC6802-1 and the LTC6802-2 data sheets and find no reason to believe that these devices are only for lead acid batteries. There is mention of "primary cell" but the data sheet also says that the cell voltage can be anywhere between zero and 5V, with specified performance for cell voltages up to 4.2V. It seems to me that the LTC6802 is well-suited to your application. I called Linear Technology [ (408)432-1900 ] and was told that this device is just a battery monitor and does not care about the battery chemistry (type of battery) and their customers are using it for all types of batteries, including super caps. I would try to get some samples and try it out. the LTC6802-1 is for daisy chaining the SPI communications, requiring fewer I/O lines on a processor than the LTC6802-2, which uses individual SPI lines so are individually addressable. the LTC6802-1 is the more popular version.

- Nick Gray

Hi, Oli -

The first thing you need to know is that interleaving of ADCs is extremely tricky. Slight differences in the signal delay along the signal lines and clock traces cause timing errors, leading to spurs in the Time Domain (FFTY) Plot. These timing differences arise primarily out of the differences in trace lengths, but also in the differences in line capacitances. Unfortunately, simulation can not show this. What you might try for simulation is putting an RC delay in the clock line to one of the ADCs to simulate this.

Scopes currently on the market use custom gigasample ADCs, the ADC083000RB/NOPB ADC083000RB/NOPB from National Semiconductor, or the TS8388B from Atmel. There may be others that I do not know about. Sometimes ADCs are time interleaved and there is some digital post processing used to minimize spurs.

The National Semiconductor ADC083000RB/NOPB ADC083000RB/NOPB is four 750 MHz ADCs time interleaved to provide 3 gigasamples per second. They have a proprietary, patented method of on-chip timing adjustment to minimize the skew problems. Atmel and National also have 10-bit gigasample ADCs and National and TI have 12-bit gigasample ADCs.

To develop low jitter clock signals, the most common method is to start with a low jitter CMOS oscillator and use a PLL-based Jitter Cleaner/Buffer. This does sound messy, but need not be so bad. As an example, the circuitry around National’s LMK series (perhaps the LMK02000 or LMK02002) is fairly simple and provides jitter down to less than 0.2 ps. The LMK03000CISQ/NOPB LMK03000CISQ/NOPB is another excellent choice.

As for links to circuits for time interleaved ADCs, I suggest you Google “Time Interleaving ADC” without the quote marks. I tried this and found a lot of information. Some information you may find especially useful includes the following two links:

http://www.analog.com/library/analogdialogue/archives/37-08/post_processing.html

http://www.google.com/url?sa=t&source=web&cd=6&sqi=2&ved=0CEAQFjAF&url=http%3A%2F%2Fciteseerx.ist.psu.edu%2Fviewdoc%2Fdownload%3Fdoi%3D10.1.1.119.6105%26rep%3Drep1%26type%3Dpdf&ei=TWjUTKfYGoK0sAPUhriNCw&usg=AFQjCNGu4mX-aI8gpGQd6GpRHo5tSMbw3g&sig2=M2qtyG22P2_LVNbcrz6irA

http://www2.spsc.tugraz.at/people/cvogel/TIADC.html

I do not think that your difficulty in finding information is so much a matter of guarding secrets, although that might have some effect, as it is in the difficulty of explaining what is happening and how to avoid the problems. The way this kind of information is passed along is from mentor to mentee in a one-on-one setting. It is difficult to pass this information on otherwise.

I do hope that you find this helpful.

- Nick