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  • Hi Marc,

     

    I am sorry but it is not possible to have, for example different areas in the board where signals can have different clearance values. You could start the DRC and "Select" an area without the MCU's area.

    I will forward your message to our development team......

     

    Regards,

    Richard

  • magooo wrote:

     

    Dear Richard,

     

    I have subscribed and regularly receive "e-mail Notifications" every time when a new message is posted in this discussion thread: Have a question about CadSoft EAGLE?  Ask our Expert, Richard!. This includes questions from users and your much valuable answers.

     

    Often I find questions & answers that are very useful for my work and I find it practical to store them as "readme files" on my computer.

    This is as simple as saving the e-mail Notification message.

     

    Unfortunately however, questions and answers are never tied toghether in the same e-mail Notification message and sometimes they are several days apart from each other. It becomes therefore difficult to find to which question an answer is related.

     

    I would like to kindly submit you the following suggestion:

    Could you please always copy ("quote") the questions in your answers?

     

    Thank you!

     

    Hi Magoo,

     

    I will try to remember to quote the messages.

     

    Regards,

    Richard

  • Richard,

    I have a couple of items that you could perhaps point me in the right direction.

     

    We have a board design with a large array of the same components...say 1600 diodes.

     

    1) Need to place these on a BRD grid of x by y spaced at nnn apart. I assume this could be done with a ULP or SCR, but I've never really looked into the programming language. Any good starting point for this specifically?

     

    2) Unfortunately when the schematic was first made, a generic diode was just picked, and used a standard part, say 1n4442.

    Now we'd like to replace them ALL with something more custom and have it in our own library where several different footprints can be tried.

    Any ideas here?

    I found a ULP that made a library for the board, but it doesn't actually make the parts on the sch/brd point to that new libraray.

  • Iain Galloway wrote:

     

    Richard,

    I have a couple of items that you could perhaps point me in the right direction.

     

    We have a board design with a large array of the same components...say 1600 diodes.

     

    1) Need to place these on a BRD grid of x by y spaced at nnn apart. I assume this could be done with a ULP or SCR, but I've never really looked into the programming language. Any good starting point for this specifically?

     

    2) Unfortunately when the schematic was first made, a generic diode was just picked, and used a standard part, say 1n4442.

    Now we'd like to replace them ALL with something more custom and have it in our own library where several different footprints can be tried.

    Any ideas here?

    I found a ULP that made a library for the board, but it doesn't actually make the parts on the sch/brd point to that new libraray.

     

     

     

    Hi Iain,

     

    There is an ULP that might help in placing matrix of components or at least giving an example for this. See the cadsoft.de download area, ULP folder. There is  matrizdeleds.ulp

     

    About the diodes: You can use the REPLACE command for this. It could be executed via a script for all diodes in the project. Syntax is:   REPLACE new_device_name component_name;

    Example:

     

    REPLACE 1N4442   D12;

    REPLACE 1N4442   D13;

    REPLACE 1N4442   D15;

     

    Regards,

    Richard

  • Richard,

     

    Thanks to your help my project is almost ready to send to the fab house.

     

    One problem I'm having is that the drc returns overlap errors everywhere I use rectangles.  I also have the problem of connecting signals of different names (sub grounds) to one point - it returns overlap errors.  Is there any way to give a rectangle a name or otherwise make it a part of a network so the drc won't return an error?

     

    Thanks,

    Mike

  • One problem I'm having is that the drc returns overlap errors everywhere I use rectangles.  I also have the problem of connecting signals of different names (sub grounds) to one point - it returns overlap errors.  Is there any way to give a rectangle a name or otherwise make it a part of a network so the drc won't return an error?

     

     

    Hi Mike,

     

    RECTs can't be connected to signals. They are non-electical objects. You could use POLYGONs instead. If you want to connect two different signals (with different names) you have to overlap two wires or two polygons....

    This will always bring up a DRC error message.

     

    Regards,

    Richard

  • Hi Richard,

     

    I study the ULP Bill of Materials and i don't know what this line is exactly doing:

    sprintf(s, "%s%-*s", line ? " " : "", Width[i], a[i]);

    What about the "%s%-*s" line ? " " : "" part of the line?

    I would be grateful if you could explain it to me that how is it works.

     

    Thanks.

  • Hi All,

                 I have downloaded new eagle V6 free version, and I tried one of my exisisting design  which is done in 5.9.0 , But afterwards I am not able to open SCH & BRD  in 5.9 .... Any idea how to do it...?

  • I don't think that's possible... 6 isn't backwards compatible. Eagle's never been very good at that. Hope you've got a backup.

    http://www.element14.com/community/thread/15752?tstart=0

  • Hi All,

                 I have  downloaded new eagle V6 free version, and I tried one of my exisisting  design  which is done in 5.9.0 , But afterwards I am not able to open  SCH & BRD  in 5.9 .... Any idea how to do it...?

    andyhunti wrote:

     

    I don't think that's possible... 6 isn't backwards compatible. Eagle's never been very good at that. Hope you've got a backup.

    http://www.element14.com/community/thread/15752?tstart=0

    Talking about backup files. There should be files for boards with the extension .b#1 up to .b#9 or the same for schematics with extension .s#1.... .s#9. You have to rename the appropriate files so that they have a valid .brd or .sch extension.

     

    Regards,

    Richard

  • I study the ULP Bill of Materials and i don't know what this line is exactly doing:

    sprintf(s, "%s%-*s", line ? " " : "", Width[i], a[i]);

    What about the "%s%-*s" line ? " " : "" part of the line?

    I would be grateful if you could explain it to me that how is it works.

    I can help a bit here, the "? :" is called a ternary operator. It's a programmer's shorthand for an if statement (if true, do something, else do something else)
    The format is  <test> ? <if true> : <if false>
    sprintf is a string formatting function, s is the string, "%s%-*s" is the format for the string operation.
    The ternary operator is returning a space if "line" is true, or nothing if "line" is false.
    So at a glance, this line inserts/writes or removes a space into the string if "line" is true.

     

    Hope this helps! I don't know how it's used in the context of the ULP, but this may give you a good idea to start from.

  • K Sz wrote:

     

    Hi Richard,

     

    I study the ULP Bill of Materials and i don't know what this line is exactly doing:

    sprintf(s, "%s%-*s", line ? " " : "", Width[i], a[i]);

    What about the "%s%-*s" line ? " " : "" part of the line?

    I would be grateful if you could explain it to me that how is it works.

     

    Thanks.

    Hi,

     

    I hope I can explain it correctly....

     

    sprintf(s, "%s%-*s", line ? " " : "", Width[i], a[i]);

     

     

    s    this is the string that will be written

    %s  belongs to  line ? " " : ""   determines whether there is a blank in the beginning of the line or not

    %-*  belongs to Width[i]          specifies the space which is reserved for the string

       s  belongs to a[i]                is a string taken from an array a[]

     

     

    Hope this helps.

    Regards,
    Richard

     

    Just saw that the message was already answered a few minutes before. Message was edited by: Richard Hammerl

  • Richard,

     

    I'm down to the silkscreen and the files must ship Friday.  Suddenly, the silk screen layers have disappeared!!  They (layers 121 and 122) do not show up in the layers list.  What have I done to make them disappear and what must I do to get them back?  I'm only slightly paniced.

     

    I'm doing two board designs and the silk screen layers show up in one but not the other.

     

    Thanks!

    Mike

  • I'm down to the silkscreen and the files must ship Friday.  Suddenly,  the silk screen layers have disappeared!!  They (layers 121 and 122) do  not show up in the layers list.  What have I done to make them  disappear and what must I do to get them back?  I'm only slightly  paniced.

     

    I'm doing two board designs and the silk screen layers show up in one but not the other.

     

    Hi Mike,

     

    please try  SET USED_LAYERS ALL;  in the command line.  Does it help?

     

    Regards,
    Richard

  • Richard,

     

    Yes, that got the silk layers back and they seem to work ok.  However, there is still weirdness.  DRC returns 1250 errors, all Stop Mask violations caused by the Names.  If I turn the tNames layer off, all those errors go away.  So it is treating the text in the tNames layer as though they are traces.  My other board project does not do this.  Is there some attribute of the Names layer that got changed, maybe?

     

    Thanks,

     

    Michael Watts

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