Hi Dusan,

please tru to open, than make ERC (OK), pinswap any port connections .................and repaet ERC (again OK) . Now UNDO and again repeat ERC - the consistency is lost and connections

mismatched in SCH

I see the problem.... forwarded to our development team.  Thanks,

Richard

Hi Richard,

I´ve got a doubt making the gerber files:

You can only place a pad in the package libraries and you can only insert the vias in the board layout. The difference between them is that a pad must be covered with cooper to join it to another track, so it must avoid the "cream frame " (green layer to protect/isolate the board), and the via don´t need that. But when I see (in the came processor) the different gerber files , specially the solder stop mask and the cream frame (layers 29,30,31,32) there is no difference between a pad and a via.

Regards,

Xabi

Hi Richard,

do you have any idea why, though the Snap length is set to 0.5mm, 6.1 leaves

tens of short airvires (0.06mm long and so) and do not connect it to the

pads??? Must be connected manually and I have to click lot of times trying

to hit the pad as exacly as possible, making unwanted bundles at the ends of

wires. What's interesting, sometimes Snap obviously works, sometimes it is

nearly impossible to finish the connection. Oh my God, have anybody tested

6.x before it was released??? Really horrible "upgrade"...

And please, do not recommend me to try beta version, I need to go forward,

not to test for free and on hot data the software I have purchased. I am now

working in both 6.1 and 5.11 and it is really a big relief to go back to

5.11, but it is quite uncomfortable to keep all data separated and not

damage anything with 6.1.

I think CadSoft have lost a lot of its good name, pity.

Dusan

Hi Xabi,

you wrote:

But when I see (in the came processor) the different gerber files ,  specially the solder stop mask and the cream frame (layers 29,30,31,32)  there is no difference between a pad and a via.

Layer 29 and 30 contain information about the solder stop mask. Each pad and smd and via will be free of lacquer by default. You can change this and have vias covered as well. (==> Design Rules, Mask tab, Limit).

Layer 31 and 32 contain information about the cream frame or solder paste mask. This on is defined for SMDs only. No pad or vias needs a solder paste.

All these is generated automatically, if you did not set this off and defined your own solder stop mask od cream frame.

Regards,

Richard

Hi Joey,

the layer setup is part of the Design Rules, which are stored in the board file. This means hat the board manufacturer can look up the setup if he would load the file in the layout editor and look into the Design Rules.

There he can find the values for thickness and the via lenghts.
But it is always good to tell the board house such details like setup and via lengths in a separate note. So I'ld recommend to tell them all details separately.

Regards,

Richard

Hi Richard,

I am affraid the Design Rules are NOT stored in brd file, at least my 6.1

doesn't store it, which in my opinion is another from long list of bugs with

potentially serious consequences...

Dusan

Hi Richard,

yes, it is what I would expect, but why if I close project and re-open it,

the Design rules are switched to default? I was surprised by the number of

errors and it is why I noticed this. Now I have to save rules in separate

file and open them after each Eagle restart - perhaps something is wrong at

my side, but I do eherything the same way I am used from past.

Dusan.

Hi Dusan,

you never bothered me..... I am glad about each message that can help in improving EAGLE.
I did some testing as well and could not find a problem with the Design Rules. So maybe you unintentionally changed the rules or loaded another dru file.

Regards,
Richard