Dual-issue mystery cycles with ARM

Help me figure this out:

I use the follow 4096 instructions on a Cortex-R4

movs r0,#1

str r0, [r8~#0]

movs r1,#2

str r1, [r8~#4]

movs r2,#3

str r3, [r8~#8]

When in "dual-issue" mode the code executes in 5162 clock cycles. ( bits 28-31 Aux control reg & bits 18-20 of the secondary Aux control register are reset.)

When dual-issue is disabled, it executes in 4146 cycles. (I saw this in ARM and Thumb2 modes)

My only thought is that dual-issue requires additional cycles of during wait stages. I have to create real-time software simulation and I am having a hard time modeling this behavior.

Thanks in advance.

Latch