Those of you who remember the old, original Star Trek TV series will recall that three-dimensional chess was a favorite pastime of Kirk and Spock about the USS Enterprise. One can only presume that by the 23rd Century the traditional two-dimensional board game had become too predictable for its practitioners.
For reasons that have more to do with solving challenges than creating new ones, the advantages gained in going from a 2D to a 3D layout has captured the attention of chip designers. On the ASICs side 3D development has centered around replacing edge wiring by creating vertical connections through the body of the chips. These through silicon vias (TSV) for interconnecting stacked devices at wafer level promise significant advantages in terms of electrical performances (signal transmission, reduced power consumption, reduced timing delays) as well as a smaller form factor.
Most recently the blogosphere has been full of reports that FPGA makers also are working diligently on developing 3D chip layouts. That makes sense for a variety of reasons, such as the ability to greatly expand gate counts. What is more, the inherent flexibility of programmable logic can come to the forefront here because it renders the “where do we place components on the 3D chip?” question a bit easier to deal with.
What do you think? How soon will we see practical, cost-effective 3D SoCs?
