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Path II Programmable

October 2019 Previous month
We are now 2 and half weeks into this challenge and I have finally got my Ultra96-V2 printing out Hello World onto the UART. This feels like a suitable point to write my first ever blog post!     Intro to course This will be a series of blog posts as I work my way through the Path II Programmable. This is a training course done by Element14 with support from Avnet and Xilinx. Who have kindly provided me with an Avnet Ultra96-v2 development board and 3 sets training modules with labs. & ...
At this stage I have gone through all the material in the Software course. It does not feel complete though as labs 9 and 11 require some additional hardware which I don’t have yet. I will not cover these two labs in this blog since I am still hoping to include more material on them in the later posts. From the remaining labs, the most important concept I learnt is how to create a complete boot image for the device on an SD card that includes: Bootloader; Power Management Unit; Main Ap ...
Lab 5 is titled Connecting SDK to Hardware. This is the first time I have had to use the dev. board since starting the Software labs. The objectives are to learn how to:   Setup the dev. board for operation Program a bitstream into the PL Configure the ARM PS over JTAGusing the TCL Run an application Debug an application   I had to connect the JTAG/UART pod to the board and set BOOT jumpers on the board to boot from JTAG.   The image below is for the Ultra96-V1 board. The ...
Path II Programmable Blog 3 - More Zynq UltraScale+ MPSoC Hardware covered videos & labs 5, 6, 7 & 8. Moving forward.     HW Chapter 9 video: Tcl Scripting  The advantages of Tcl scripting which include sharing projects (since the script alone can rebuild the project) and quick rebuilds (since you don't need to use the GUI to set parameters).   HW Lab 9 - The Power of Scripting using Tcl  Executed the provided Tcl script which removed some blocks (JTAG-AXI) ...
In this post, I will briefly cover the hardware labs 3, 4, and 5 for Path II Programmable.   Lab 3 - Memory and peripherals test This lab walked through manually adding peripherals like SD interfaces, I2C, SPI, UART, GPIO, and Display Port. The training is really geared towards teaching an embedded engineer how to custom-tailor Vivado settings for a specific implementation of the MPSoC chip on a custom board. This means that we have to manually configure clock speeds for each peripheral a ...
I saw that hackster.io is offering the Avnet Ultra96 Technical Training Courses as a bundle for a reduced price.  This includes the 3 introductory courses that are used for Path II Programmable plus 3 advanced courses.  Of course, you need to bring your own hardware, but I thought this might be of interest for people following this training.   https://www.hackster.io/workshops/ultra96 ...
This blog covers the next set of Zynq HW videos, some of which I have already blogged about at Path II Programmable Blog 2 - An Introduction to Zynq UltraScale+ MPSoC Hardware On the whole, this training material is the same as Path to Programmable v1, except with a couple of changes where the Zynq MPSoc differs from Zynq-7000   HW Chapter 5 video: Merging the PS and the PL  Interfacing the PL to the PS using different AXI interfaces An Introduction to AXI Cache coherency features ...
Developing Zynq MPSoC Hardware   I decided to start with the Zynq MPSoC Hardware courses - most of it seemed very similar to Zynq-7000 which was covered in Path to Programmable, so I'm hoping that I will be able to get through all of the material quickly.   HW Chapter 1 video: The Case for a System-on-Chip This video was about: the advantages of parallel processing and how it can overcome the bottlenecks in most software caused by sequential processing. a dual-chip solution (proces ...
This week has been more productive than the last since much of the first week was spent configuring the development infrastructure.  I have completed the 10 HW videos (lectures) and the 9 HW labs and the 12 SW videos and 11 SW labs.  I use the term "completed" somewhat loosely because a couple of the labs (HW 8 and SW 11) use the mezzanine board kit which we did not receive so I went through all the steps but could not verify the results on the hardware other than through the debugger. ...
Creating an SD Boot Image  This lab was very straightforward, but I ran into an issue that left me scratching my head for a while.   This lab used the previously created "Test_Peripherals" application to build the SD card boot image. This test application ran with no issues in JTAG debug mode in lab 5.   I walked through the steps of creating the boot image, including adding the PMU firmware. Generated the BIN boot image and loaded it up on the Ultra96-V2 board. The terminal ou ...
Path II Programmable - An Introduction   Continuing from where Path to Programmable left us with Zynq-7000 training, it's time to explore Zynq UltraScale+ MPSoC with Path II Programmable! Zynq UltraScale+ MPSoC follows in the footsteps of Zynq-7000 with a more powerful PS, and a larger & faster PL - learning how to use it is going to be very interesting.   The Training Material   The course content that Randall shared seems to be the same as the 3 introductory Ultra96 Tech ...
Hello! This is the first of multiple posts in Path II Programmable training lessons from Element14, Xilinx, and Avnet. I participated in Path [1] to Programmable exactly 1 year ago, and was fortunate to be chosen for the second in the series. This year's training comes with a much fancier board - the Ultra96 version 2. Last time around we had the MiniZed, which is well capable in its own rights.   For those interested, here is a link to the training that I did last year: Path to Programm ...
cmelement14

Week #2

Posted by cmelement14 Oct 26, 2019
HW Lab 7 - Create Custom IP Lesson Learned - Case Sensitive Problem A Missing Field? Duplicated Lines Mystery Folder HW Lab 8 - Walk Around without Mezzanine Board Amazing Hardware Debugger & Built-in Logical Analyzer Missing Menu Item? HW Lab 9 - Incorrect Line Numbers Referred in Lab Instruction SW Lab 1 to 3 - Preparation SW Lab 4 - Explore Further - A Failed Memory Test Mismatch between Instruction and Screenshot Create an Extra Memory Test A ...
These first few labs have been about getting up and running on the Xilinx SDK and getting familiar with the SDK environment.   SDK First Impressions   The SDK is built on the Eclipse IDE platform. I have had very little interaction with Eclipse in the past, but I'm liking it quite a bit already. To an inexperienced user, it's hard to tell what features are native Eclipse and what features have been added in by Xilinx. Overall, the feel and design flow seems user-friendly and intuitiv ...
It's been a little over 10 minutes (according to my cellphone's clock) since I clicked "Launch SDK"  from Vivado and the progress bar is almost halfway filled. I'm following the tutorials in the "MPSoC_HW_2018_3_student_complete" zip file, the "Lab_instructions" directory.  This is lab 2, page 24. This is on a machine with and Intel Core I7-3770 rated at 3.4 Ghx, 16 GB of memory running Ubuntu 18.04.3 LTS 64-bit. Seriously????? I'm supposed to create software with tools that have g ...
Lab 1 is very simple and helps you get familiar Zynq MPSoC hardware platform. Avnet uses a pre-built archived hardware platform to show you the ropes. They use an HDF file, which I have never seen before. The file is written out from Vivado. It contains the information needed to develop software application with SDK. A couple the files in the archive included an html used by Xilinx that acts as a datasheet for the HW platform and hwh file in XML format that contains information the SDK uses to b ...
IntroThis is the first time I publish something on element14 – so I am bit nervous but very excited about the journey, as we follow the three courses on developing for Zynq MPSoC. It took a while to ship the ULTRA96-V2 kit from Chicago to the UK, so I only spent around 5 days with the board by now. The training program consists of three core modules – Software, Hardware and Petalinux. I decided to focus on the software course to begin with and have now completed 3 out of 11 labs, whi ...
cmelement14

Week #1

Posted by cmelement14 Oct 19, 2019
Introduction Lab 0 - Pr-requisite Problem of Xilinx JTAG + Serial [0700] HW Lab 1 - Inconsistent Folder Format HW Lab 2 - Tip for Mapping I/O Pins HW Lab 3 - Probably Missing a Step HW Lab 6 - Slightly Different Conclusion Summary   Introduction  First of all, thank our sponsors Xilinx and  Avnet for offering this Path II Programmable training opportunity. Also thank rscasny for selecting me as one of the trainees. In general, the training ma ...
dcsoutherner

Getting Started

Posted by dcsoutherner Oct 19, 2019
I'll be using the Xilinx software tool chain on a Linux host and not using a VM running on a Windows workstation.  I'm choosing this because the project i have in mind requires interaction between the Ultra96 and a software defined radio device which is currently controlled by a linux-based control program.  I'll be using Ubuntu 18.04 LTS on a roughly 10 year old computer. Like some others I'l be using the latest version of the Xilinx tool chain, the SDSoC 2019.1 which I'm downloading ...
I was amazed at the huge amount of lesson material associated with Path II Programmable.  I ended up with around 10GB in 18 zip archives.  As I mentioned in my earlier blog, the training program is a combination of 3 Avnet Ultra96 courses.  With all this material it would have been nice to have an overview document that provided a roadmap of how to navigate the course and a list of all the course material.  To be fair, the documentation is very good and it just takes some stu ...
Hope please add your experience and study materials so that it will help for not selected people to learn out of your experience. ...
I'm finally up and running with the development environment and Xilinx tools. The training material was serious when it mentioned the Ubuntu virtual machine (VM) installation would take a significant amount of time!   The VM instructions were thorough and detailed for the most part; however, there were a few items which weren't explicitly stated. In the network bridging section it said to select "Bridged Adapter" in order to connect the VM to the Internet via my computer's network hardware ...
I installed the Vivado and Xilinx SDK tools along with Petalinux using the instructions from the link: http://avnet.me/AvnetTTC_VM  [Oracle® VM VirtualBox Installation Instructions for Windows and Linux Virtual Machine Creation Targeting Avnet Development Boards] They use versions of the tools from 2018. However, I installed the 2019.1 version of everything including Petalinux. I modified a few things unique to me. It was mostly error free however I ran into an issue with the Petalinu ...
ralphjy

The Challenge Begins

Posted by ralphjy Top Member Oct 14, 2019
Wow.  I've been looking through the course material and it is quite comprehensive.  It's actually 3 Avnet courses combined into a one training package.   Developing Zynq MPSoC Hardware (10 lectures, 9 labs) Developing Zynq MPSoC Software (12 lectures, 11 labs) Integrating Sensors on Ultra96 with PetaLinux (7 lectures, 6 labs)   Quite a lot of material to cover in a month.  Looking forward to the challenge and a lot of learning .   HW Agenda   SW Agenda &# ...
I installed the Vivado tools in Windows when I went through other tutorials in preparation for the training. However, Ubuntu is used in training given the use of PetaLinux. I found the latest PetaLinux Tools Documentation Reference Guide UG1144 (v2019.1) May 22, 2019 which states that Ubuntu Linux 16.04.5, 18.04.1 (64-bit) is the current supported Ubuntu version. I found the version of Ubuntu here: Index of /releases ...
I downloaded all the materials for the Path II Programmable training yesterday. I am using Google Keep to organize my schedule. It makes it easier for me to check off what I have done and track my progress. The agenda below is pretty straight-forward and thorough. I have completed the completed the videos for chapters 1, 2, 3 and 4. I cannot seem to find the labs in question above so I am going to bounce to the developing hardware training videos and do the labs for hardware.The videos so far ...