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This blog is continuing on with the rest of hardware labs.   Lab 5: Adding a PL Peripheral  In this lab, we added our first PL peripheral to the hardware design. We added an AXI BRAM controller which allows the processing system to access the programmable logic block ram via an AXI interface, giving the PS yet another source of memory (in addition to the on-chip memory and DDR4 memory on the Ultra96-V2 board). The Xilinx AXI BRAM controller IP allows for configuring AXI protocol, numbe ...
My project will involve routing a video stream through a neural network element and deriving detection, control and display outputs from the Ultra96v2, so I've been looking for examples that will help me learn how to accomplish this.  Unfortunately there are a lot of examples for the ZCU102 and the Ultra96v1 but it seems only a few specifically for the Ultra96v2.  I found a project on Hackster:  https://www.hackster.io/gaihrekrishna/dpu-trd-for-ultra96-22e426 which used the Ultra9 ...
Ina previous lab I learnt scripting using tcl. This lab expands on the concept by teaching me how to do more complex automation using tcl. I used tcl scripting to finalize the hardware project to be used in developing Zynq MPSoC Software. IN this lab I learnt how to:   • Source a Tcl script • Understand the power of scripting • Understanding of the hardware platform that will be used in the Developing Zynq MPSoC Software TTC   TCL scripting was used to build the d ...
IP created is tested via simulation as well as in hardware. Embedded designs like Zynq MPSoC requires software to be written to test IP. The LogiCORE IP JTAG-AXI core was added in a previous last lab and the core was customized. It can generate AXI transactions and drive AXI signals internal to the MPSoC at run-time. It was used to test the IP. The JTAG-AXI core uses the Vivado Logic Analyzer and pre-built software was used to validate our test. The software application included an Interrupt Ser ...
Vivado has large IP catalog which makes it very easy to connect many of the common interfaces to designs. This lab provided step-by-step instructions on how to create custom IP, add it to the IP catalog, and then connect it to a design. The IP that we added was a Pulse Width Modulation (PWM) controller. It takes clock, duty cycle, and period inputs to create a PWM output as well as a count output. The IP generates an Interrupt when an invalid PWM range is written into block. The PWM was used to ...
Can anyone suggest a cheap usb webcam for the Ultra96V2 that has drivers for petalinux? I need it for my final project. Thanks, Cary ...
The next element that I need to tackle for my embedded vision project is the creation of accelerated vision processing IP using Vivado HLS and the xfOpenCV function library.  That would allow me to create a component that I could include in my design.  There are a lot of examples of this but it was much harder to accomplish process than I expected.  I found a Hackster project that essentially demonstrated what I wanted to do Accelerating Image Processing with Ultra96  https:/ ...
filupgasinthevan

P2P: HW Labs 1-4

Posted by filupgasinthevan Nov 23, 2019
With the software labs complete, it was time to move on to hardware. I think it was recommended that we start with software first, but I think hardware first (the path most P2P trainees chose) probably made more sense. In the software labs, we imported hardware definitions which were then used to create the board support package, etc. This becomes the platform for the software development side of MPSoC design. This hardware definition was created in Vivado.   The Vivado tool can be thought ...
In this lab the BRAM added from the previous lab is used to buffer data going between the PS and PL.  A software application that enables the PS DMA engine was used to show the efficiency gains achieved by passing data between the PL-based BRAM and external DDR4 memory. I learnt how to: • Create a new C Software Application and import C source code • Use PS DMA and GIC controllers • Perform DMA operations using the PS DMA   The workspace and software was pre-writ ...
In this lab I expanded the block design by extending the memory space with a PL-based Block RAM (BRAM). The BRAM was used to buffer data going between the PS and PL. I learnt how to: • Add a BRAM from the IP Catalog • Connect AXI peripherals to the Zynq MPSoC PS.   You add IP using the + or ADD IP option from the menu.   The IP is called an AXi BRAM. It was configured for the Ultra96-V2 hardware.   One of the good things about Vivado is that it has a alot of ...
This lab gave am an introduction to Tool Command Language (TCL) commands that can be run to modify and archive a project. I learnt how to: • Open and close block designs using TCL • Execute simple TCL commands to manipulate IP Integrator block designs • Export a block design to a TCL file on disk     Access to the TCL Console is front and ccenter in Vivado   I was able to open a project and even add and remove ports on my block design just using tcl script ...
The object of this  Lab was to learn how to: •Enable and map all default peripherals in IP Integrator • Set the PS clocks for the PS peripherals and the PL • Create and Run C programs   It involved enabling and mapping all the PS peripherals needed. This was done using the I/O configuration. I used it to setup and configure the SD Card interface, I2C, GPIOs, SPI, UART and the system clocks. It was fairly straight forward to setup the clocks and PLLs needed. ...
Lab 1: Vivado includes all the required tools for creating new FPGA and SoC designs as well as the Software Development Kit (SDK) for developing software. The Zynq MPSoC Processing System (PS) has a configurable set of built-in peripherals as well as direct access to Programmable Logic (PL) that can build any custom IP. The PS may be used without anything programmed in the PL. However, in order to use any soft IP in the PL, or to route PS dedicated peripherals to device pins in the PL, programmi ...
vladrumyan

P2P Hardware Module

Posted by vladrumyan Nov 20, 2019
IntroductionIn this blog I will go over the Hardware module of the Ultra96-V2 training. I will change my approach slightly compared to my Software posts: instead of going through each lab, I will cover the main concepts I learnt form the lab exercises and lectures. So, here are the 2 things I want to talk about this time: IP Integrator; AXI interface debugging. IP IntegratorSince it is more and more common for PL and PS to be combined within one module, knowing how to work with IP Integrator ...
The goal of this lab was to familarize us with the SPI communication between the Ultra96-V2 and a Click Mezzanine sensor; the  LMS6DSL 6 degrees of freedom sensor. https://www.st.com/content/st_com/en/products/mems-and-sensors/inemo-inertial-modules/lsm6dsl.html   At the end of the lab I learnt how to: • Create a bare metal BSP and import application files into SDK • Add libraries to your standalone applications • Run and explore the SPI communication with the Cl ...
Having completed the 3 Avnet Ultra96 courses in the Path II Programmable training, it's now time to move on to creating a project with what we have learned.  I know what I would like to do conceptually but I doubt that I can successfully implement it in the 5 week time frame we have for  the project.  Even though there are a wealth of examples in the Xilinx ecosystem, one thing I definitely learned from the courses are that there are huge issues with hardware and software version ...
The first set of Petalinux videos & labs were covered in Path II Programmable Blog 8 - Getting started with Integrating Sensors on Ultra96 with PetaLinux. Continuing...   Petalinux Chapter 5 video: Sensor Intro  Expansion ports on the Ultra96. A recap of Mikroelectronika click boards & the Ultra96 click mezzanine.     PetaLinux Lab 5 - IoT Application: Log Sensor Data to IBM™ Bluemix  Created a new project for the lsm6dsl and imported a source file whi ...
I've completed the hardware & software courses, so now it is time for the last bit - using Petalinux to build Linux for Zynq & accessing hardware from an application.       Petalinux Chapter 1 video: Overview, Review of Ultra96 Kit, PetaLinux Overview  An overview of what's bundled with the Ultra96. What else we need: power supply, debugger, mezzanine board etc. An Introduction to Petalinux - a collection of tools for building Linux for Zynq on x86. How Petalinu ...
Lab 8: SDK Project Management  Continuing along with the training, Lab 8 walked through archiving the various elements of an SDK project, including the project source files, run/debug configurations, breakpoints, and workspace settings. Most of it is as easy as File -> Export, but the workspace settings require a little more manual effort. This is all done to allow projects to be easily shareable, since zipping the project and sharing it is likely to not work. Once the archives were cre ...
The development time of applications can be reduced by taking advantage of libraries of reusable code. Xilinx provides libraries that can be built into a BSP as a selectable option. In this lab we I used is the Xilinx Fat File System for demonstration of the concept.This library enables application to create, modify and read files. The labs uses the Fat File System to store data on an SD card reuse.   The application provided with the lab uses the internal ADC of the MPSoc to monitor the d ...
I have now finished all the training content for Path II Programmable!   In this series, we are provided an Ultra96 board and a series of training modules focused around three areas - Hardware (the FPGA side), Software (the microprocessor side), and Petalinux (the OS side).   Updates There are six lessons for the PetaLinux modules in this training program. They center around running a special blend of Linux directly on the Ultra96 board. We are taught how to get files on and off, build ...
The goal of this lab was to learn: • How to enable the interrupt subsystem to allow hardware interrupts to interrupt software execution • Create an interrupt service routine to handle the hardware interrupt   An interrupt handler, also known as an Interrupt Service Routine (ISR), is a callback subroutine in microcontroller firmware, operating system, or device driver whose execution is triggered by the reception of a hardware interrupt. Interrupt handlers have a multitude of ...
Introduction Lab 1 - A Couple of Lessons Learned Lab 2 - Redundant Constrain Files & Possible Missing Steps in Lab Instruction Lab 3 - Wifi Setup & Network/Internet Access Lab 4 - Remote Debug Linux Application Lab 5 - IoT Application Lab 6 - Discrepancies in Lab Instructions Conclusion     Introduction  The is the last part of my training before building my own project. It blogs all PetaLinux training labs (Lab 1 to Lab 6). The first lab g ...
In this series, we are provided an Ultra96 board and a series of training modules focused around three areas - Hardware (the FPGA side), Software (the microprocessor side), and Petalinux (the OS side).   In this blog post, I'll outline the Software lessons 6 through 12. There was a lot covered, so I'll be brief.   Lab 06 - First Stage Bootloader In this lab, we create the First Stage Bootloader (FSBL). This is needed as a first step to running our application as stand-alone on the Ult ...
In this lab you are advised not to share or archive your workspace simply by zipping it up and sending it off. In my FPGA designs at work the verilog designs are foten shared among two engineers while the software for the SOC FPGa desing is done by one of three software engineers. So it is very common to have mutiple peopleworkingon the same project and sharing the design envirnoment and porject come in handy.   Workspaces are just a container of software projects, and your preferences are ...
Week 4 involved finishing up the PetaLinux labs and getting prepared for the post training project.   I received the Click Mezzanine Stater kit https://www.newark.com/avnet/aes-acc-u96-me-sk/aes-acc-u96-me-sk-rohs-compliant/dp/03AH7038?st=ultra96%20click%20mezzani… this week and was able to complete Labs 4-6.   The labs use the temperature sensor on LSM6DSL Click which is interfaced using SPI.  Below is the LSM6DSL Click on the Mezzanine board mounted on the Ultra96. &# ...
With the FSBL and PMU firmware done in Lab 06, Lab 07 involved learning how to create a boot image and boot one of my applications from non-volatile memory. A complete boot-up typically of the Zynq requires four things:   1. FSBL 2. PMU Firmware 3. Bitstream 4. Application   The lab showed me how to combine those four things pieces to create the boot image for the microSD Card. At the end of the lab I was bale to: • How to create a boot image • Boot from SD Card  ...
Today, I was able to get a lot of progress with the SW lessons 0-5 In this series, we are provided an Ultra96 board and a series of training modules focused around three areas - Hardware (the FPGA side), Software (the microprocessor side), and Petalinux (the OS side). I got some new kit!Thanks a bunch to the E14 guys and everyone from Avnet/Xilinx supporting this training. Today, I got the 96Boards Click Mezzanine Click Starter kit. This comes with the Mezzanine with spots for two Click Boards, ...
Today I finished up the Hardware series with Lab 09 - TCL Scripting In this series, we are provided an Ultra96 board and a series of training modules focused around three areas - Hardware (the FPGA side), Software (the microprocessor side), and Petalinux (the OS side).   Lab 09 - TCL Scripting This is a quick blog post since the lab was very quick. We simply open the project that we had going from Lab 08 and run a script. This script has been highly customized for this training to take the ...
Week 3 marks my start of the PetaLinux course.  Before I did that I needed to move the Xilinx development environment to another more powerful computer.  I now consider it somewhat of a miracle that I was able to get through the HW and SW courses using an i3 computer with 8GB of memory.  I moved the setup (VM and XIlinx tools) to a new i7 with 16GB of memory.  Setting up the VM for a second time went quickly and this time I installed Ubuntu 16.04.4 to insure that I was compat ...
I think post, I will discuss the latest set of labs in the Path II Programmable series. In this series, we are provided an Ultra96 board and a series of training modules focused around three areas - Hardware (the FPGA side), Software (the microprocessor side), and Petalinux (the OS side).   Lab 06 - Improving  flow between the PS and PL The outcome of this lab is to describe the differences in how we can architect our system for the best performance; namely the speed of memory trans ...
In Lab 5, I learnt how to use the SDK JTAG connection and a TCL script to initialize the ARM processor registers and debug applications. However, in this lab initialization of the ARM processor was done in an embedded fashion using code called the First Stage Boot Loader or FSBL. One of the great things about Vivado is the amount of automation it does for the developer. The FSBL is one of those functions that the Xlininx SDK automatically creates using a template. The SDK interprets the hardware ...
This blog post completes the Zynq MPSoC software training, most of which has been covered in Path II Programmable Blog 5 - Starting with Zynq UltraScale+ MPSoC Software with Xilinx SDK  and Path II Programmable Blog 6 - More Zynq UltraScale+ MPSoC Software with Xilinx SDK   SW Chapter 9 video: Interrupts  An introduction to hardware & software interrupts. A look at the interrupt interface on Zynq MPSoc - multiple sources and multiple endpoints. The GICs are configurable and ...
Continuing from Path II Programmable Blog 5 - Starting with Zynq UltraScale+ MPSoC Software with Xilinx SDK with software lectures/labs 5,6,7 & 8:   SW Chapter 5 video: Connecting Hardware & Debugging  An overview of the hardware on the Ultra96v2. Xilinx Configurations - a bunch of settings associated with a run or debug 'profile'. It controls how the system is reset, programmed, setup and offers a bunch of other settings. Xilinx System Debugger is an improved version of the ...
In Path II Programmable Blog 4 - Finishing off with Zynq UltraScale+ MPSoC Hardware, I completed the hardware courses. Now, it's time for the 'Developing Zynq MPSoC Software Lectures'.   SW Chapter 1 video: Zynq MPSoC System Architecture Basics  The plan for the software courses - what will be covered & how it can be used. Looked at Zynq MPSoC architecture once again (PS processors, video codes, security features etc.) This video was mostly a recap.   SW Lab 1 - Exp ...
cmelement14

Week #3

Posted by cmelement14 Nov 2, 2019
SW Lab 6 - Zynq UltraScale+ MPSoC Boot Process SW Lab 7 - The Release Version of Test_Peripheral Application Doesn't Work. SW Lab 8 - Import & Export SDK Workspace Content SW Lab 9 - LED Light Control SW Lab 10 - File System Library SW Lab 11 - Access SPI Device     SW Lab 6 - Zynq UltraScale+ MPSoC Boot Process  SW lab 6 & 7 are about the boot process for Zynq UltraScale+ MPSoC devices. It is the most complicated boot process I have encountered so ...
ralphjy

P2P: WiFi Driver issue

Posted by ralphjy Top Member Nov 2, 2019
I ran into a problem when I was first doing the Ultra96 hardware quickstart where I could not reliably connect my iPad to the Ultra96 WiFi access point.  At that time I just bypassed it by configuring as a WiFi client.   Now I have that same problem when going through the PetaLinux labs and decided to look into it.  It turns out that the 2018.3 BSP that I am using has the incorrect WPA driver specified.  Apparently this is an issue that others have encountered before: Can't ...
Continuing my week2 post......  this will cover the SW introductory course   The objectives for the introductory Software course are: Introduce developers to Xilinx SDK (Software Development Kit) Demonstrate SDK capabilities Connect SDK to hardware for execution and debug Utilize a peripheral interrupt to show real-time software response Show a basic example of how to use an external sensor module   This diagram shows the handoff of the hardware design from Vivado to the SD ...
SW Lab 7 Problem Description A Correct SW Lab 7 Solution     SW Lab 7 Problem Description  Like other people reported here and there, I noticed the same problem in Experiment 2, SW Lab 7: the peripheral test application stuck at the point of showing message "Running Interrupt Test  for psu_csudma..." (shown in the screenshot below).   However, we did a similar peripheral test application in Experiment 3, SW Lab 5. The only difference between them is: in lab ...