In this labs I have learnt about how to configure the PS according with the platform that is going to be used, add IP from the Xilinx catalogue and create your custom IP. Further, the power of the TCL scripting is explained and I realized how to do some task following the right work flow.

 

From lab 1 to lab 6

I had never configured the PS IP block before (preset configuration), I always used the base block design that the board vendor usually supplies when you acquire the development kit. So that, thanks to this tutorial I have learnt a lot about how to configure properly the PS IP and I realized the which peripherals can be connected to MIO and which one can be connected to the EMIO.

 

Once the PS has been configured, our design is ready to add new IP blocks. It is wonderful how Vivado does the standard connection automatically, it save lot of time and avoid very common mistakes. But, after the labs it is still no clear for me the difference about generating the output product as general, as out of context per ip or out of context per block-design.

 

During the labs, a really good trick was mentioned. Once the hardware has been exported to the SDK, if you do some changes and need to export it again, it is necessary to create a new folder for the new exportation, because sometime the project in the SDK tool can fail.

 

There are some TCL commands that are very useful when the block design is finished. You can export your project and a TCL script is automatically created with all the information about the project configuration and the block design diagram. It is very useful if you want to share your project with other colleagues or upload to your repository. I usually run this script when my block design has no error and I want to save my project in my control version repository.

 

From lab 7 to lab 9

 

The lab 7 is the most complete lab in this chunk of tutorials. Here you can create your custom hardware, create an IP block from the hardware and then use it into your block design. The process for the IP packaging is very automatic, so it is helpful but I realized when you are in the packaging process, in the Files Group step, you have to ensure that all files of the IP have to be in the right synthesis order, if they are not, the synthesis process will fail due to some modules cannot be found. So, we should to come back to the IP packaging process, reorder the files, pack the IP again, reset the output product, generate them again and launch the synthesis process.

 

The most important discovery for me through this labs has been the JTAG-AXI IP. This IP can easily be added to a design and you can use easily TCL commands to run read and write transactions to and from any AXI-based slave peripheral in you design. I have only experimented the command used on the lab, but I'm sure that there are much more commands with lot of options. I would like to know if this IP could be used form AXI Stream interfaces, it would be awesome.