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Path II Programmable

11 Posts authored by: avnrdf
Continuing on from where I left off in Path II Programmable Blog 10 - Project Part 1 - Exploring PYNQ with the Ultra96v2 ...   IP to capture waveforms to, and generate waveforms from BRAM:  I created a new IP that can capture data from an input interface to BRAM, and transfer data from BRAM to an output interface. I won't go into too many details about how it works on the inside, but it's pretty simple: An AXI-4 Lite slave interface that exposes 3 registers: 3 inputs (PS to IP) and 1 ...
The Path II Programmable training covered a great deal of Zynq MPSoC Hardware, Software and Petalinux content - covering almost everything required to build a Zynq MPSoC system: right from the logic running to the PL, to Petalinux and software applications that run on the PS. My plan was to work on a project that covered all of this, but this turned out to be more complicated that I originally thought it would be. To add to this, I've been very busy at work, so there have been a couple of weeks ...
The first set of Petalinux videos & labs were covered in Path II Programmable Blog 8 - Getting started with Integrating Sensors on Ultra96 with PetaLinux. Continuing...   Petalinux Chapter 5 video: Sensor Intro  Expansion ports on the Ultra96. A recap of Mikroelectronika click boards & the Ultra96 click mezzanine.     PetaLinux Lab 5 - IoT Application: Log Sensor Data to IBM™ Bluemix  Created a new project for the lsm6dsl and imported a source file whi ...
I've completed the hardware & software courses, so now it is time for the last bit - using Petalinux to build Linux for Zynq & accessing hardware from an application.       Petalinux Chapter 1 video: Overview, Review of Ultra96 Kit, PetaLinux Overview  An overview of what's bundled with the Ultra96. What else we need: power supply, debugger, mezzanine board etc. An Introduction to Petalinux - a collection of tools for building Linux for Zynq on x86. How Petalinu ...
This blog post completes the Zynq MPSoC software training, most of which has been covered in Path II Programmable Blog 5 - Starting with Zynq UltraScale+ MPSoC Software with Xilinx SDK  and Path II Programmable Blog 6 - More Zynq UltraScale+ MPSoC Software with Xilinx SDK   SW Chapter 9 video: Interrupts  An introduction to hardware & software interrupts. A look at the interrupt interface on Zynq MPSoc - multiple sources and multiple endpoints. The GICs are configurable and ...
Continuing from Path II Programmable Blog 5 - Starting with Zynq UltraScale+ MPSoC Software with Xilinx SDK with software lectures/labs 5,6,7 & 8:   SW Chapter 5 video: Connecting Hardware & Debugging  An overview of the hardware on the Ultra96v2. Xilinx Configurations - a bunch of settings associated with a run or debug 'profile'. It controls how the system is reset, programmed, setup and offers a bunch of other settings. Xilinx System Debugger is an improved version of the ...
In Path II Programmable Blog 4 - Finishing off with Zynq UltraScale+ MPSoC Hardware, I completed the hardware courses. Now, it's time for the 'Developing Zynq MPSoC Software Lectures'.   SW Chapter 1 video: Zynq MPSoC System Architecture Basics  The plan for the software courses - what will be covered & how it can be used. Looked at Zynq MPSoC architecture once again (PS processors, video codes, security features etc.) This video was mostly a recap.   SW Lab 1 - Exp ...
Path II Programmable Blog 3 - More Zynq UltraScale+ MPSoC Hardware covered videos & labs 5, 6, 7 & 8. Moving forward.     HW Chapter 9 video: Tcl Scripting  The advantages of Tcl scripting which include sharing projects (since the script alone can rebuild the project) and quick rebuilds (since you don't need to use the GUI to set parameters).   HW Lab 9 - The Power of Scripting using Tcl  Executed the provided Tcl script which removed some blocks (JTAG-AXI) ...
This blog covers the next set of Zynq HW videos, some of which I have already blogged about at Path II Programmable Blog 2 - An Introduction to Zynq UltraScale+ MPSoC Hardware On the whole, this training material is the same as Path to Programmable v1, except with a couple of changes where the Zynq MPSoc differs from Zynq-7000   HW Chapter 5 video: Merging the PS and the PL  Interfacing the PL to the PS using different AXI interfaces An Introduction to AXI Cache coherency features ...
Developing Zynq MPSoC Hardware   I decided to start with the Zynq MPSoC Hardware courses - most of it seemed very similar to Zynq-7000 which was covered in Path to Programmable, so I'm hoping that I will be able to get through all of the material quickly.   HW Chapter 1 video: The Case for a System-on-Chip This video was about: the advantages of parallel processing and how it can overcome the bottlenecks in most software caused by sequential processing. a dual-chip solution (proces ...
Path II Programmable - An Introduction   Continuing from where Path to Programmable left us with Zynq-7000 training, it's time to explore Zynq UltraScale+ MPSoC with Path II Programmable! Zynq UltraScale+ MPSoC follows in the footsteps of Zynq-7000 with a more powerful PS, and a larger & faster PL - learning how to use it is going to be very interesting.   The Training Material   The course content that Randall shared seems to be the same as the 3 introductory Ultra96 Tech ...