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About:Through Avnet, Xilinx and Element14, a training program to learn about the Zynq 7000 platform which is System On Chip combining an FPGA with an ARM processor. This comes to the students as complete development board packed with goodies like a wireless chip from MuRata (BT/BTLE/WIFI), 8GB Flash memory, onboard RAM, USB to JTAG (JTAG programmable over USB), Arduino-style headers (3.3V compatible only), Microphone, Bi-Color LED, and two additional expansion ports.   See all blog posts fo ...
The lab 4 gives us basic knowledge how to use Tool Command Language commands in Vivado e.g. to create scripts which could execute several steps. Main points of this lab: - TCL commands for open/close block designs, - simple TCL commands to manipulate IP integrator block designs, - exporting a block design to TCL file.   We need to launch Vivado and and from Window menu choose option: Tcl Console. In this console we could check current working directory with command pwd. After that we c ...
The Lab 3 is continuation of previous Lab. In this part we will learn how to set up additional peripherals like QSPI, USB and SD. From the SDK point of view we will learn how to use example test applications.   First step is customization of Zynq ARM core by enabling QSPI, USB and GPIO in Vivado block design. It could be done from MIO Configuration page from ZYNQ7 PS. At the end we need to re-launch synthesis, implementation and generation of bitstream. After that we could export a hardwar ...
Note: This is part 3 of a series on working with FPGAs and in particular the Xilinx Zynq-7000S Programmable System-on-Chip with ARM Cortex-A9 processing core. For all parts, click here: Path to Programmable   For part 1, click here: Xilinx ZYNQ System-on-Chip - Getting to know the MiniZed Board For part 2, click here: Xilinx ZYNQ - Blog 2 - Getting Code Running on the SoC   Introduction Establishing a Design Process/Work Flow Configuring SPI Flash and USB Configuring ...
mu.udhay

Hello World with Minized

Posted by mu.udhay Oct 28, 2018
First of All , Sorry for long Pause Guys ! I missed you So much I would Make sure to Pace up with the Rest ASAP.   Installing Xilinx Vivado in Linux:   First of All , Get Ready with Required Tools: Xilinx Vivado(2017.4 or Later version only) , EDK , Drivers(for Windows) , Putty or Tera Term   Note: XIlinx Vivado support only for 64 bit Architecture, So check for it before getting Started.   For Linux folks , I made my First Video on how to install it .     ...
The main purpose of lab number 2 is configuration of the Zynq processing system to use UART peripheral to run example Hello World application.   1. Enabling and configuration of a UART peripheral The Zynq SoC has MIO pins divided into two banks: Bank 0 = MIO0-15 and Bank 1 = MIO16-53. We need to set voltage for these banks to LVCMOS 3.3V. Additionally we need to enable UART1 peripheral and map it to MIO[48:49]. To do that we need to double-click on Zynq PS. On Page called MIO Configuratio ...
Out of curiosity, I decided this weekend to spend some time to measure the heat distribution on the Minized FPGA board and compare it to another fpga board. For this measurement I used the FLIR ThermoVision A20M 60Hz 160 x 120 Infrared Thermal Imaging Camera IR Imager. It was a fun experiment to do. Datasheet of the ThermoVision A20M   Introduction to ThermoVision A20M The Test Setup The Results of the Thermal Imaging Test Conclusion   Introduction to ThermoVision A2 ...
The MiniZed training is getting more complicated.  Several new items have been discussed including TCL, AXI, DMA, and BRAM.  Lab 3 objectives: This lab is designed to set up the hardware configuration in Vivado and the SDK for the actual components and features found on the MiniZed board. This is similar to the include file for a microprocessor GPIO mapping you would use with a typical compiler, although much more complicated. There is a nice "wizard" type interface with tabbed ...
The main purpose of this lab is to illustrate how to create a new Zynq project using UltraFast Design Methodology within Vivado Webpack.   Zynq Proccesing System (PS) has a configurable set of built-in peripherals and direct access to Programmable Logic (PL) that can build any custom IP. So, I we need we could create dedicated soft IP in PL and use it in PS.   1. Create a new Zynq project in Vivado Below there is gallery with step-by-step instructions how to create a new project. Ea ...
The main purpose of this laboratory is configuration of environment for the development. It based on Windows PC environment and have three main steps: - downloading and installation of Xilinx Vivado WebPACK, - downloading and installation of Tera Term, - obtaining and extracting the appropriate Speedway training files archive.   I am using Linux environment and had already installed Xilinx Vivado WebPACK in version 2018.2. I described installation process here: Xilinx Spartan-7 FPGA Mak ...
mconners

Lab 4 - TCL me Xilinx

Posted by mconners Top Member Oct 25, 2018
Lab 4 - Using TCL in Vivado Embedded Designs   This lab was pretty simple, the goal was to exercise the Vivado environment via the command line using TCL. TCL is the Tool Command Language. It was invented by John Ousterhout at UC Berkeley in 1998. It was intended to unify command languages. It grew in popularity when it was adopted by Sun Microsystems. I remember hearing about TCL and TK in the nineties as a way to add GUI functionality to command line programs. That kind of seems what the ...
Note: This is part 2 of a series on working with FPGAs and in particular the Xilinx Zynq-7000S Programmable System-on-Chip with ARM Cortex-A9 processing core. For part 1, click here: Xilinx ZYNQ System-on-Chip - Getting to know the MiniZed Board For all parts, click here: Path to Programmable   Introduction Creating an Example Project Zynq-7000 Programmable Logic and DSP Scale Exploring Vivado Adding the Processor System Configuring the Processing System Configur ...
In this week; I also completed Lab 3, Lab 4 and Lab 5. The objectives of these labs were also very well written and rather simple to follow. These labs are a continuation from previous labs which can be found here   Lab 3 Lab 4 Lab 5 Conclusion   Lab 3  Main Objectives of this blog • Enable and map all default peripherals in IP Integrator • Set the PS clocks for the PS peripherals and the PL • Create and Run C programs Peripheral Tests ...
About:Through Xilinx and Element14, a training program to learn about the Zynq 7000 platform which is System On Chip combining an FPGA with an ARM processor. This comes to the students as complete development board packed with goodies like a wireless chip from MuRata (BT/BTLE/WIFI), 8GB Flash memory, onboard RAM, USB to JTAG (JTAG programmable over USB), Arduino-style headers (3.3V compatible only), Microphone, Bi-Color LED, and two additional expansion ports.   See all blog posts for this ...
Introduction Lab0 Lab1 Lab2   Introduction  As I had already mentioned in my application I have worked with FPGAs in the past for 2 years roughly including my masters thesis with the old Xilinx ISE. So I kind of have a basic sense of how FPGAs work and the background behind them. At the time I had also worked with Microblaze which was quite a sensation when the idea of soft-processor was amazing. It has become quite main-stream in the FPGAs today though. So one can say ...
Overview :   This lab is similar to the previous lab, we configured some additional peripherals, export to the SDK, and exercise the newly created peripherals.       Notice in the above diagram, there are checks next to UART 1, GPIO, SD 1, USB 0,  and QUAD SPI. One of the important lessons they wanted us to learn in this lab was why the order in which you map peripherals matters. The devices are listed in priority in the green boxes above, with the memory devices ha ...
Path To Programmable - Lab 1  About: Through Xilinx and Element14, a training program to learn about the Zynq 7000 platform which is System On Chip combining an FPGA with an ARM processor. This comes to the students as complete development board packed with goodies like a wireless chip from MuRata (BT/BTLE/WIFI), 8GB Flash memory, onboard RAM, USB to JTAG (JTAG programmable over USB), Arduino-style headers (3.3V compatible only), Microphone, Bi-Color LED, and two additional expansion ports. ...
Well I had to spend a week on-site with a customer and another week at a trade show; but I'm back!   I'm happy to report that I got Vivado 2017.4 installed. I followed the instructions in this "experiment" to install the dev environment... although I was a little worried why Xilinx considers installing software an experiment...   I started by creating an account on the Xilinx website. It was a little tricky since they don't trust the apostrophe in my last name... The story of my li ...
So, I'm not one of the Path to Programmable trainees, but I decided to get a MiniZed and try to follow along with everyone else's blogs. I'm a hitchiker on the Path to Programmable. Anyone care to join me?   I'm hoping that there will be enough info disseminated by the bloggers to help me along the path with them. And thanks to kk99, I've also got an Arty S7 which should make thing easier if I'm "just" looking at the FPGA side of things. FPGAs are looking fun so far and I found a good Veri ...
The PetaLinux provides a reference Linux distribution which is integrated and tested for Xilinx devices. This distribution includes: - boot loader, - CPU-optimized kernel, - Linux applications and libraries, - Debug, - Thread and FPU support, - Web server for easy management of network or firmware configuration.   After plug in of the micro-USB cable to the USB0JTAG/UART port on the MiniZed board we are able to login to PetaLinux. Here are serial connection parameters: - Port: COM1, ...
Here are the objectives for the first few labs:     The instructions were very clear, although I'm not sure of all the why yet, I managed to output some ASCII The lab pdfs link to a 790pg technical reference manual for your reading pleasure.....ug585-Zynq-7000-TRM.pdf Once Vivado and the SDK are configured for the MiniZed hardware, the actual code is minimal. Time to watch some more videos...... ...
Introduction The Path to Programmable training course is intended to help users get up-to-speed using Xilinx parts containing programmable logic and an ARM application processor core inside. These parts are known as Xilinx Programmable System-on-Chip or SoCs. The Xilinx ZYNQ-7000 series is their cost-optimized range.   Using a programmable SoC in theory can make a lot of sense for certain embedded use-cases, because it can act a lot like a custom processor chip. The programmable logic can ...
mconners

Finally got the Board

Posted by mconners Top Member Oct 14, 2018
OK, the board finally arrived, although a day later than expected, due to Hurricane Michael, fortunately the storm hit quite a bit to the west of me, so I am not dealing with hurricane aftermath.       This was a nice little guide to the board that was inside the package.   Lab exercise:   The first lab exercises mostly revolved around getting familiar with the vivado tools, as well a a customized version of Eclipse. We were brought into a Block Design configuration ...
dotmish

Module 1 - Lesson 1

Posted by dotmish Oct 8, 2018
P2P – Module 1 – Lesson 1 Notes  Introduction  This is an introductory video that is about 9 minutes in length.  The training is branded as AVNET “Speedway”, and is taught by Josh Foster.  The module 1 objectives are:   Understand how to use Vivado's tools with the Zynq-7000. Learn about the integrated ARM Cortex A9 processor core. Use the Xilinx embedded tools to design and build a system - including both the integration of pre-built IP modul ...
dotmish

Module 1 - Overview

Posted by dotmish Oct 8, 2018
Module one includes a series of video lectures.  Here's the overview:     There are a total of 11 video lectures:   I will be posting my notes for each of the video lectures. ...
While I am reading the necessary Dokus I thought it would be a good idea to look into some basics of the MiniZed FPGA board and what it offers to the users and potential programmers.   When compared to other suppliers FPGAs development board such as from Digilent; the Avent MiniZed is reasonably priced at 80 euros (rather low end price). And can be bought off the internet easily. A good amount of support documentation also exists on the MiniZed | Zedboard Support Forum for self starters. ...
Last Thursday I finally received the MiniZed development board from Element14. Many thanks to the community and the element14 judges for selecting me as one of the participants. The development board was well packed and came in with some essential info on to-dos and don'ts with the MiniZed board. A humble USB cable for powering and some jumpers if needed I would guess.   As advertised the MiniZed ZYNQ kit should include the following things in the box   The Unboxing and Test &# ...
Hi Guys this is my first Post ,My Board is about to come, may be within 24 hrs ,My Peers have already shared their Nice Experiance with it , So inorder to prevent Redundency I would like to give a brief Overview regarding the Purpose of the Board , How it's Architecture would be , What you can do with it   First of All What is Minized PSoC ? Minized is Xilinx Zynq XC7Z007S based Programmable SoC (System on Chip) , which has a  Processor Subsystem (PS) of ARM Cortex A9 core and the ...
I received an email with instructions for downloading the first MiniZed training package.  The overview and Lab0 are mostly about product specifications and features. I watch the first two videos, and I am instructed to do Lab1.  Here's where it gets interesting.  Lab1 starts out using Vivado 2017.1, or 2017.4, and I just spent 2 days installing 2018.2.1 43.6GB ! To be continued...... ...
Today I have received package with the MiniZed Zynq development board. Here are pictures of this board: What is in the box: - two layers of protection foam, - USB2.0 to micro USB wire, - three jumpers, - safety guide and instruction, - voucher for Xilinx Software Design Tool product, - the MiniZed Zynq Development Board The board is really small. On the top of board there are: - expansion shield, - two pmod expansion, - USB to JTAG/Debug UART, - USB 2.0 host interface, - ST Mic ...