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HW Chapter 2 video: Xilinx Embedded Tool Flow The presenter first went over the different Vivado Design Suite editions: WebPACK is free and supports the common Zynq devices that are found on most development boards (7010 and 7020), and the more expensive HL System & Design editions which support additional features like Partial Reconfiguration & System Generator for DSP. The next slide summarized the typical workflow of Zynq Development. The hardware designer uses Vivado, the IP Integra ...
Introduction  Path to Programmable is a training course for Programmable SoCs, like the the Xilinx Zynq-7000 All Programmable SoC. As many others have pointed out, this isn't a typical FPGA/HDL course, since the training material focuses less on the digital design/FPGA aspect, but is more about using Xilinx tools (like IP based design etc) - many of which will be relevant for other non-SoC FPGAs in the Xilinx portfolio and some might apply only to Zynq (PS-PL interconnects etc.). In line ...
All my previous blogs can be read in detail here Path to Programmable This blog is further continued from Week 5: Done!! Lab 8 A good read of the previous blog 8 is necessary to understand this Lab 9 as they are related in the project context.   Aim of the Lab 9 Blog Finish Hardware Build using Tcl Look into the .xdc file Power Utilization of the project Final Device and Schematics Conclusion   Aim of the Lab 9 Blog  In lab 9 we explore the benefits of ...
All my previous blogs can be read in detail here Path to Programmable  This blog is further continued from Week 4: Done!! Lab 7 A good read of the previous blog 7 is necessary to understand this Lab 8 as they are related in the project context.   Lab 8 Overview and Objectives Experiment 1: Testing the software that handles PL-generated interrupts and utilizes an Interrupt Service Routine The Test Results for LED dimmer control at PL LED via software in SDK Experiment 2: ...
In this Post , we will get helpful insights about an IP (Intellectual Property) , How we can create our Own , How we can Integrate it in Our Design using powerful  Xilinx Vivado tools. For Some Motivation about IP just see the below diagram of the Design I implemented in Vivado for working on PWM in Minized: As you can see , the Above Design consists of various blocks Such as "ZYNQ_7 Processing System" Block,"AXI Interconnect "Block,"PWM_w_int" block etc.. All these blocks are simply the ...
We left off last time after creating new IP and adding some debug ports. We added a PWM module, a logic analyzer, and a JTAG port.     This week we got to exercise those pieces.   First thing we did was export the hardware to the SDK workspace and created an empty application.     So we created the LED_Dimmer_Int program. We just added existing source from the provided source files directory. You might be able to make out the PWMIsr method there. This is a console ...
About:Through Avnet, Xilinx and Element14, a training program to learn about the Zynq 7000 platform which is System On Chip combining an FPGA with an ARM processor. This comes to the students as complete development board packed with goodies like a wireless chip from MuRata (BT/BTLE/WIFI), 8GB Flash memory, onboard RAM, USB to JTAG (JTAG programmable over USB), Arduino-style headers (3.3V compatible only), Microphone, Bi-Color LED, and two additional expansion ports.   See all blog posts fo ...
These are notes from the module 1 – chapter 2 Speedway video lecture.   Tools and tool flow.   The Vivado Design Suite WebPACK edition is free and it supports seven Zynq devices.  The free tools include a simulator, device programmer, logic analyzer, serial I/O analyzer, debugger, and design synthesis and integration tools. The typical design flow is to have a system architect responsible for the overall design, with software and hardware developers/designers performing t ...
dotmish

Back After Some Issues

Posted by dotmish Nov 21, 2018
Hi everyone,   Sorry that I've been absent for a while.  Had some significant personal and family health issues.  Then last week Western PA got slammed with a huge ice storm.  A huge amount of trees fell.  We had trees fall on our propane tank, car, and house.  Fortunately damage was minor.  But a lot of work getting everything cut up.   We had no power for 3 days, and no Internet for 5 days.  And even though our Internet connection has been restore ...
During roadtest of Arty S7 I have created a simple PMOD module with single segment display. So, I decided to use it with MiniZed SoC to create example application. I have a driver for single segment display written in Verilog. I used a top module to generate test pattern for this display module. ZYNQ7 processing system is required in this case in design to generate system clock used by top and display modules. Seven segment display is connected to PMOD1 connector. There are pinouts: - L15 -> ...
snidhi

Week 4: Done!! Lab 7

Posted by snidhi Nov 20, 2018
All my previous blogs can be read in detail here Path to Programmable   This lab was very special and interesting. It involved creating a custom ip block (partly in VHDL and partly in GUI) and adding it to the existing previous vivado design with the BRAM memory. In this lab we actually did some VHDL programming. In this lab one can see that the ip creation in VHDL itself is quite some work and understanding of the input; output signals in the ip block is necessary.   Lab 7 Overvie ...
snidhi

Week 4: Done!! Lab6

Posted by snidhi Nov 20, 2018
In the previous weeks I finished the lab 6 and lab 7 together.   Lab 6 Theme & Main Objectives Testing Lab 6 with the serial port Conclusion   In lab 6 I learned how to establish the data flow between the programmable logic PL and processing system PS using the PS DMA. The PS DMA controller improves data transfer between PS and PL. This lab 6 is pretty easy to be done and continues from lab 5.   Lab 6 Theme & Main Objectives  In the last lab 5, PL-bas ...
Note: This is part 4 of a series on working with FPGAs and in particular the Xilinx Zynq-7000S Programmable System-on-Chip with ARM Cortex-A9 processing core. For part 1, click here: Xilinx ZYNQ System-on-Chip - Getting to know the MiniZed Board For all parts, click here: Path to Programmable   Introduction Using Tcl Tcl Basics Basic Stuff Doing maths Using if-else statements Using while statements Using for loops File input/output Saving and Recreati ...
I spent the weekend figuring out Lab 9.  It turns out that my file system wasn't in line with the TCL script.  The instructions are as follows: ***NOTE*** If you receive an error running the Tcl command above please delete your entire ZynqDesign project and ip repo. Then start from Experiment 1 step 1 in which you unzip a pre-built lab 8 project and ip repo to the correct location. The reason you received an error was most likely due to an incorrect naming convention that was done in ...
I have finished Lab 7! This one was quite a bit longer for me and took three or four nights to get through.   About:Through Avnet, Xilinx and Element14, a training program to learn about the Zynq 7000 platform which is System On Chip combining an FPGA with an ARM processor. This comes to the students as complete development board packed with goodies like a wireless chip from MuRata (BT/BTLE/WIFI), 8GB Flash memory, onboard RAM, USB to JTAG (JTAG programmable over USB), Arduino-style headers ...
Hello Everyone, My peers in Path to Programable have Done Great work in giving step by step procedure to implement DMA transfer so Why Reinvent the Wheel , I take a different approach. I will try to present a vivid picture regarding Why we need to implement few IPs to achieve DMA transfer between BRAM and DDR instead of using PS and How? First As always we take Bottom Up approach , Fasten your Seat Belts !   What is DMA ? DMA refers to Direct Memory Access , which in short is used to re ...
So far this has been the most challenging lab, mostly because of the amount of typing. We added a PWM module with an interrupt. If you've been following along, you'll see that during this lab we added the portion outlined in red.         So we added the PWM module that we created, a Logic Analyzer from the built in IP, and a JTAG interface, also from the built in IP.   As you start to go through the process of creating the new IP, you are asked a few questions, and u ...
The objectives of Lab 7: https://www.xilinx.com/products/intellectual-property.html The basic objective of the last few labs in this training module is to light up an LED and control it with a PWM output. In addition, the JTAG interface was explored, along with ILA debugging.  A few hours into this session, I could enter a number into a terminal program, and the LED would change brightness from off to full-on.  The ILA is a logic analyzer GUI that utilizes the dual-port m ...
In this lab we are use a TCL scripts to prepare and finalize our hardware project.   We will use here a lab9.tcl script delivered in Speedway support documents. Please go to the following directory: ZynqHW/2017_4/Support_documents/Lab9/ and type source ./lab9.tcl This scripts is responsible for adding a new IP blocks do design like Wireless Manager or GPIO. It creates proper connections then regenerate the layout and perform synthesis and implementation followed by bitstream generation ...
In this lab we will learn how to use a hardware debugging interface to to perform run-time interactions with IP cores.   1. Adding a IP JTAG-AXI core to the design Please select Add IP and choose JTAG to AXI Master Core from IP catalog. After that please run connection automation. After that we could add a LED constraints to PWM_w_Int IP. Please right click on LED[0:0] pin located on the PWM_w_Int_v1.0 IP then select crate port. Now please select option Add Sources from Flow Navigat ...
In this lab we will learn how to create a custom IP, add it to the IP catalogue and use it in the design.   1. How to create a new AXI peripheral Please select from main bar option: Tools->Create and Package IP New IP. There will appear a wizard. Please select option to create a AXI4 peripheral. Enter package name, display name and description. Default interface settings are fine for this module. Press Finish. New IP will be added to IP catalog. 2. Modify the new IP Proj ...
Hello Folks !   We are now in the funniest part ! Believe me Guys , i gone through the basics of the tcl at first this week , studying how it works and what are possible pitfalls and various others along with why it is used in Vivado , how it is implemented in Vivado.   In this post i would like to give better insights regarding tcl and vivado tcl (Yeah , there is a voltage difference between the two )   Firstly the TCL (but i remember the TICK show)   Most of you guys a ...
In this lab we will enable PS DMA engine to improve data flow between PL-based BRAM and external DDR3 memory.   We will base on project from lab 5. We need to launch SDK. Then we need to check if in system.hdf there is present BRAM IP block. Now please create a new application project with empty application. Then we need to import test application called: dma_test.c provided in course materials. Now we could program FPGA device and launch on hardware. There is a simple applicati ...
In this lab we will create a Block RAM in the programmable logic which can be used to buffer data going between the PS and PL.   1. How to add BRAM from IP Catalog Open block design with ZYNQ7 processing system. Choose the Add IP button on the shortcut bar of the diagram. From the IP Catalog select option AXI BRAM Controller. Double click the AXI BRAM Controller and customize IP. We need to increase Data Width to 64 bits and change Support for AXI Narrow Bursts to Manual. Then click OK ...
I have finished Labs 4, 5, and 6!   About:Through Avnet, Xilinx and Element14, a training program to learn about the Zynq 7000 platform which is System On Chip combining an FPGA with an ARM processor. This comes to the students as complete development board packed with goodies like a wireless chip from MuRata (BT/BTLE/WIFI), 8GB Flash memory, onboard RAM, USB to JTAG (JTAG programmable over USB), Arduino-style headers (3.3V compatible only), Microphone, Bi-Color LED, and two additional expa ...
HI guys ! This post is mainly Intended to Answer few Important Questions regarding why we are doing few things for Getting your Project Runing on Minized at First. Here are the List of Questions this Post aims to Clarify,If you got few other Questions as well, Feel free to ask,I will make sure to give vivid picture regarding it. NOTE : These Questions are actually created by guessing possible doubts users would encounter regarding my Previous post of "Hello World with Minized".   Quest ...
mconners

Labs 5 & 6

Posted by mconners Top Member Nov 3, 2018
Finally starting to access the PL   I grouped labs 5 & 6 together because they really are 2 parts of a single lab. Lab 5 was adding a Block Ram to the Processing System using the AXI Interconnect System, Lab 6 was actually Programming the FPGA to create the IP, and the second half was compiling a program and installing it on the CPU to execute some DMA tests, record the timings, and calculate the speed savings using Interrupt DMA. One of the enlightening things about this lab was seein ...
I've been really enjoying following along with Path to Programmable - both with the blogs on here and the Avnet Speedway course that seems to be an earlier version of P2P.   One thing I have found so far is that "Path to Programmable" is a slightly misleading title. I'm new to FPGAs. Completely new. I was hoping to get a good intro to FPGAs by following this, but that's not really been the case.   The Path to Programmable looks good but it seem to be all about the transition from FPG ...