Finally starting to access the PL


I grouped labs 5 & 6 together because they really are 2 parts of a single lab. Lab 5 was adding a Block Ram to the Processing System using the AXI Interconnect System, Lab 6 was actually Programming the FPGA to create the IP, and the second half was compiling a program and installing it on the CPU to execute some DMA tests, record the timings, and calculate the speed savings using Interrupt DMA. One of the enlightening things about this lab was seeing all of the different types of IP designs they provide for you. I'm not sure of the exact number, but they have FFT and DFT blocks, FIFO's, Ethernet Blocks, Video Frame Buffers, Processor Cores, and much, much more.





If you look at some of my earlier blogs, you may remember that the above diagram only contained the ZYNQ7 Processing System. In the lab we added the Reset Block, the AXI Interconnect, the BRAM Controller, and the Block Memory Generator. It's a lot of steps so I won't go through them here, but it's not a difficult process to add each of the components. I did not have to draw the interconnect lines, it did that when I added each of the blocks. So that was nice. It also took care of arranging the blocks for me.




The above is a screenshot of the SDK. They had a pre written program to exercise the Block Memory they had us add. We did make use of a new button this time. Right below the help link, there is a button with a red arrow and 3 green boxes. We clicked on that to program the FPGA. After that we hooked up the console below. Flashed the processor, and exercised the newly added IP.




In the above example, I had chosen an 8192 block size for a DMA transfer of BRAM to BRAM, which resulted in 24x improvement over having the CPU copy the data.



The above screen capture is more of the same. I pretty much tried all the combinations.


That's it for Labs 5 & 6. Really just a baby step that we will build on. Lab 7 is about creating Custom IP so that should be a bit more interesting.


I am enjoying this, and I'm glad I'm remembering what we did in previous labs, so their technique  is working. The material and exercises are not particularly difficult, but the ZYNC7 processor is a very complex device. There are a lot of possible configurations and uses so we'll see where this goes.


That's all for now. If you have questions, feel free to ask.