I have finished Labs 4, 5, and 6!

 

About:

Through Avnet, Xilinx and Element14, a training program to learn about the Zynq 7000 platform which is System On Chip combining an FPGA with an ARM processor. This comes to the students as complete development board packed with goodies like a wireless chip from MuRata (BT/BTLE/WIFI), 8GB Flash memory, onboard RAM, USB to JTAG (JTAG programmable over USB), Arduino-style headers (3.3V compatible only), Microphone, Bi-Color LED, and two additional expansion ports.

 

See all blog posts for this training here.

 

Lab 4 explains a lot more about the TCL ("Tickle") interface.

The lesson focused around creating some VHDL files which can used to create easy backups of your project; then exporting them from Vivado. These can be easily used by Source Control programs to create the backup and documentation as they are flat text files. They can then later on be re-imported to generate a new project which has all the same specs as the original one.

 

We can open a project with the command shown below:

open_project ./ZynqDesign.xpr

 

When we type the ./ then the TCL interface becomes interactive and shows the user in flyout menus the director tree. This is similar to intellitype with Microsoft Visual Studio and many other IDEs for creating software. This was very useful since the files I was opening were about 30 folders deep in my file structure.

 

Opening the Board Design was very similar with the following command:

open_bd_design ./ZynqDesign.srcs/sources_1/bd/Z_system/Z_system.bd

 

 

I was able to export the board design in a simialr manner -

 

write_bd_tcl basic_design.tcl

and export the project using

write_project_tcl -paths_relative_to C:/Speedway/ZynqHW/2017_4/ZynqDesign project_setup.tcl

 

 

And of course there is interactve help from this command line interface as well -

help write_project_tcl

 

Between the board file and the project, the entire contents of the Vivado project are captured in two relatively small text files. They look like C code and, when executed by reading them in, they re-create the project. This is why they are useful for source control - one can easily make a tcl file and do a check-in. Then anyone else can perform a check-out and import the two files then be off and running.

 

Here is the output of my Project_Setup.tcl file:

#*****************************************************************************************
# Vivado (TM) v2017.4 (64-bit)
#
# project_setup.tcl: Tcl script for re-creating project 'ZynqDesign'
#
# Generated by Vivado on Wed Oct 31 23:09:15 -0500 2018
# IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017
#
# This file contains the Vivado Tcl commands for re-creating the project to the state*
# when this script was generated. In order to re-create the project, please source this
# file in the Vivado Tcl Shell.
#
# * Note that the runs in the created project will be configured the same way as the
#   original project, however they will not be launched automatically. To regenerate the
#   run results please launch the synthesis/implementation runs as needed.
#
#*****************************************************************************************
# NOTE: In order to use this script for source control purposes, please make sure that the
#       following files are added to the source control system:-
#
# 1. This project restoration tcl script (project_setup.tcl) that was generated.
#
# 2. The following source(s) files that were local or imported into the original project.
#    (Please see the '$orig_proj_dir' and '$origin_dir' variable setting below at the start of the script)
#
#    "C:/Users/Jaymzo1/Documents/Element14/ZynqHW_Lab3_Solution/ZynqDesign/ZynqDesign.srcs/sources_1/bd/Z_system/hdl/Z_system_wrapper.vhd"
#
# 3. The following remote source files that were added to the original project:-
#
#    <none>
#
#*****************************************************************************************


# Set the reference directory for source file relative paths (by default the value is script directory path)
set origin_dir "C:/Users/Jaymzo1/Documents/Element14/ZynqHW_Lab3_Solution/ZynqDesign"


# Use origin directory path location variable, if specified in the tcl shell
if { [info exists ::origin_dir_loc] } {
  set origin_dir $::origin_dir_loc
}


# Set the project name
set project_name "ZynqDesign"


# Use project name variable, if specified in the tcl shell
if { [info exists ::user_project_name] } {
  set project_name $::user_project_name
}


variable script_file
set script_file "project_setup.tcl"


# Help information for this script
proc help {} {
  variable script_file
  puts "\nDescription:"
  puts "Recreate a Vivado project from this script. The created project will be"
  puts "functionally equivalent to the original project for which this script was"
  puts "generated. The script contains commands for creating a project, filesets,"
  puts "runs, adding/importing sources and setting properties on various objects.\n"
  puts "Syntax:"
  puts "$script_file"
  puts "$script_file -tclargs \[--origin_dir <path>\]"
  puts "$script_file -tclargs \[--project_name <name>\]"
  puts "$script_file -tclargs \[--help\]\n"
  puts "Usage:"
  puts "Name                   Description"
  puts "-------------------------------------------------------------------------"
  puts "\[--origin_dir <path>\]  Determine source file paths wrt this path. Default"
  puts "                       origin_dir path value is \".\", otherwise, the value"
  puts "                       that was set with the \"-paths_relative_to\" switch"
  puts "                       when this script was generated.\n"
  puts "\[--project_name <name>\] Create project with the specified name. Default"
  puts "                       name is the name of the project from where this"
  puts "                       script was generated.\n"
  puts "\[--help\]               Print help information for this script"
  puts "-------------------------------------------------------------------------\n"
  exit 0
}


if { $::argc > 0 } {
  for {set i 0} {$i < [llength $::argc]} {incr i} {
    set option [string trim [lindex $::argv $i]]
    switch -regexp -- $option {
      "--origin_dir"   { incr i; set origin_dir [lindex $::argv $i] }
      "--project_name" { incr i; set project_name [lindex $::argv $i] }
      "--help"         { help }
      default {
        if { [regexp {^-} $option] } {
          puts "ERROR: Unknown option '$option' specified, please type '$script_file -tclargs --help' for usage info.\n"
          return 1
        }
      }
    }
  }
}


# Set the directory path for the original project from where this script was exported
set orig_proj_dir "[file normalize "$origin_dir/"]"


# Create project
create_project ${project_name} ./${project_name} -part xc7z007sclg225-1


# Set the directory path for the new project
set proj_dir [get_property directory [current_project]]


# Reconstruct message rules
# None


# Set project properties
set obj [current_project]
set_property -name "default_lib" -value "xil_defaultlib" -objects $obj
set_property -name "dsa.num_compute_units" -value "60" -objects $obj
set_property -name "ip_cache_permissions" -value "read write" -objects $obj
set_property -name "ip_output_repo" -value "$proj_dir/${project_name}.cache/ip" -objects $obj
set_property -name "part" -value "xc7z007sclg225-1" -objects $obj
set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj
set_property -name "simulator_language" -value "Mixed" -objects $obj
set_property -name "target_language" -value "VHDL" -objects $obj
set_property -name "xpm_libraries" -value "XPM_FIFO XPM_MEMORY" -objects $obj


# Create 'sources_1' fileset (if not found)
if {[string equal [get_filesets -quiet sources_1] ""]} {
  create_fileset -srcset sources_1
}


# Set 'sources_1' fileset object
set obj [get_filesets sources_1]
# Import local files from the original project
set files [list \
 "[file normalize "$origin_dir/ZynqDesign.srcs/sources_1/bd/Z_system/hdl/Z_system_wrapper.vhd"]"\
]
set imported_files [import_files -fileset sources_1 $files]


# Set 'sources_1' fileset file properties for remote files
# None


# Set 'sources_1' fileset file properties for local files
set file "hdl/Z_system_wrapper.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj




# Set 'sources_1' fileset properties
set obj [get_filesets sources_1]
set_property -name "top" -value "Z_system_wrapper" -objects $obj


# Create 'constrs_1' fileset (if not found)
if {[string equal [get_filesets -quiet constrs_1] ""]} {
  create_fileset -constrset constrs_1
}


# Set 'constrs_1' fileset object
set obj [get_filesets constrs_1]


# Empty (no sources present)


# Set 'constrs_1' fileset properties
set obj [get_filesets constrs_1]


# Create 'sim_1' fileset (if not found)
if {[string equal [get_filesets -quiet sim_1] ""]} {
  create_fileset -simset sim_1
}


# Set 'sim_1' fileset object
set obj [get_filesets sim_1]
# Empty (no sources present)


# Set 'sim_1' fileset properties
set obj [get_filesets sim_1]
set_property -name "top" -value "Z_system_wrapper" -objects $obj




# Adding sources referenced in BDs, if not already added




# Proc to create BD Z_system
proc cr_bd_Z_system { parentCell } {


  # CHANGE DESIGN NAME HERE
  set design_name Z_system


  common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..."


  create_bd_design $design_name


  set bCheckIPsPassed 1
  ##################################################################
  # CHECK IPs
  ##################################################################
  set bCheckIPs 1
  if { $bCheckIPs == 1 } {
     set list_check_ips "\ 
  xilinx.com:ip:processing_system7:5.5\
  "


   set list_ips_missing ""
   common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."


   foreach ip_vlnv $list_check_ips {
      set ip_obj [get_ipdefs -all $ip_vlnv]
      if { $ip_obj eq "" } {
         lappend list_ips_missing $ip_vlnv
      }
   }


   if { $list_ips_missing ne "" } {
      catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n  $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
      set bCheckIPsPassed 0
   }


  }


  if { $bCheckIPsPassed != 1 } {
    common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above."
    return 3
  }


  variable script_folder


  if { $parentCell eq "" } {
     set parentCell [get_bd_cells /]
  }


  # Get object for parentCell
  set parentObj [get_bd_cells $parentCell]
  if { $parentObj == "" } {
     catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
     return
  }


  # Make sure parentObj is hier blk
  set parentType [get_property TYPE $parentObj]
  if { $parentType ne "hier" } {
     catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
     return
  }


  # Save current instance; Restore later
  set oldCurInst [current_bd_instance .]


  # Set parent object as current
  current_bd_instance $parentObj




  # Create interface ports
  set DDR [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR ]
  set FIXED_IO [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 FIXED_IO ]


  # Create ports


  # Create instance: processing_system7_0, and set properties
  set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 ]
  set_property -dict [ list \
   CONFIG.PCW_ACT_APU_PERIPHERAL_FREQMHZ {666.666687} \
   CONFIG.PCW_ACT_CAN_PERIPHERAL_FREQMHZ {10.000000} \
   CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ {10.158730} \
   CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ {10.000000} \
   CONFIG.PCW_ACT_ENET1_PERIPHERAL_FREQMHZ {10.000000} \
   CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ {10.000000} \
   CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ {10.000000} \
   CONFIG.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ {10.000000} \
   CONFIG.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ {10.000000} \
   CONFIG.PCW_ACT_PCAP_PERIPHERAL_FREQMHZ {200.000000} \
   CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ {200.000000} \
   CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ {25.000000} \
   CONFIG.PCW_ACT_SMC_PERIPHERAL_FREQMHZ {10.000000} \
   CONFIG.PCW_ACT_SPI_PERIPHERAL_FREQMHZ {10.000000} \
   CONFIG.PCW_ACT_TPIU_PERIPHERAL_FREQMHZ {200.000000} \
   CONFIG.PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ {111.111115} \
   CONFIG.PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ {111.111115} \
   CONFIG.PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ {111.111115} \
   CONFIG.PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ {111.111115} \
   CONFIG.PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ {111.111115} \
   CONFIG.PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ {111.111115} \
   CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ {100.000000} \
   CONFIG.PCW_ACT_WDT_PERIPHERAL_FREQMHZ {111.111115} \
   CONFIG.PCW_ARMPLL_CTRL_FBDIV {40} \
   CONFIG.PCW_CAN_PERIPHERAL_DIVISOR0 {1} \
   CONFIG.PCW_CAN_PERIPHERAL_DIVISOR1 {1} \
   CONFIG.PCW_CLK0_FREQ {10000000} \
   CONFIG.PCW_CLK1_FREQ {10000000} \
   CONFIG.PCW_CLK2_FREQ {10000000} \
   CONFIG.PCW_CLK3_FREQ {10000000} \
   CONFIG.PCW_CPU_CPU_PLL_FREQMHZ {1333.333} \
   CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0 {2} \
   CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0 {15} \
   CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1 {7} \
   CONFIG.PCW_DDRPLL_CTRL_FBDIV {32} \
   CONFIG.PCW_DDR_DDR_PLL_FREQMHZ {1066.667} \
   CONFIG.PCW_DDR_PERIPHERAL_DIVISOR0 {2} \
   CONFIG.PCW_DDR_RAM_HIGHADDR {0x1FFFFFFF} \
   CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0 {1} \
   CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR1 {1} \
   CONFIG.PCW_ENET0_RESET_ENABLE {0} \
   CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR0 {1} \
   CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR1 {1} \
   CONFIG.PCW_ENET1_RESET_ENABLE {0} \
   CONFIG.PCW_ENET_RESET_ENABLE {0} \
   CONFIG.PCW_EN_CLK0_PORT {0} \
   CONFIG.PCW_EN_CLK1_PORT {0} \
   CONFIG.PCW_EN_CLK2_PORT {0} \
   CONFIG.PCW_EN_CLK3_PORT {0} \
   CONFIG.PCW_EN_EMIO_SDIO1 {0} \
   CONFIG.PCW_EN_GPIO {1} \
   CONFIG.PCW_EN_QSPI {1} \
   CONFIG.PCW_EN_SDIO1 {1} \
   CONFIG.PCW_EN_UART1 {1} \
   CONFIG.PCW_EN_USB0 {1} \
   CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR0 {1} \
   CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR1 {1} \
   CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR0 {1} \
   CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR1 {1} \
   CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR0 {1} \
   CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR1 {1} \
   CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR0 {1} \
   CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR1 {1} \
   CONFIG.PCW_FCLK_CLK0_BUF {FALSE} \
   CONFIG.PCW_FCLK_CLK1_BUF {FALSE} \
   CONFIG.PCW_FCLK_CLK2_BUF {FALSE} \
   CONFIG.PCW_FCLK_CLK3_BUF {FALSE} \
   CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100} \
   CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {150} \
   CONFIG.PCW_FPGA3_PERIPHERAL_FREQMHZ {25} \
   CONFIG.PCW_FPGA_FCLK0_ENABLE {0} \
   CONFIG.PCW_FPGA_FCLK1_ENABLE {0} \
   CONFIG.PCW_FPGA_FCLK2_ENABLE {0} \
   CONFIG.PCW_FPGA_FCLK3_ENABLE {0} \
   CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1} \
   CONFIG.PCW_GPIO_MIO_GPIO_IO {MIO} \
   CONFIG.PCW_I2C0_RESET_ENABLE {0} \
   CONFIG.PCW_I2C1_RESET_ENABLE {0} \
   CONFIG.PCW_I2C_PERIPHERAL_FREQMHZ {25} \
   CONFIG.PCW_I2C_RESET_ENABLE {0} \
   CONFIG.PCW_IOPLL_CTRL_FBDIV {42} \
   CONFIG.PCW_IO_IO_PLL_FREQMHZ {1400.000} \
   CONFIG.PCW_MIO_0_DIRECTION {inout} \
   CONFIG.PCW_MIO_0_IOTYPE {LVCMOS 3.3V} \
   CONFIG.PCW_MIO_0_PULLUP {enabled} \
   CONFIG.PCW_MIO_0_SLEW {slow} \
   CONFIG.PCW_MIO_10_DIRECTION {inout} \
   CONFIG.PCW_MIO_10_IOTYPE {LVCMOS 3.3V} \
   CONFIG.PCW_MIO_10_PULLUP {enabled} \
   CONFIG.PCW_MIO_10_SLEW {slow} \
   CONFIG.PCW_MIO_11_DIRECTION {inout} \
   CONFIG.PCW_MIO_11_IOTYPE {LVCMOS 3.3V} \
   CONFIG.PCW_MIO_11_PULLUP {enabled} \
   CONFIG.PCW_MIO_11_SLEW {slow} \
   CONFIG.PCW_MIO_12_DIRECTION {inout} \
   CONFIG.PCW_MIO_12_IOTYPE {LVCMOS 3.3V} \
   CONFIG.PCW_MIO_12_PULLUP {enabled} \
   CONFIG.PCW_MIO_12_SLEW {slow} \
   CONFIG.PCW_MIO_13_DIRECTION {inout} \
   CONFIG.PCW_MIO_13_IOTYPE {LVCMOS 3.3V} \
   CONFIG.PCW_MIO_13_PULLUP {enabled} \
   CONFIG.PCW_MIO_13_SLEW {slow} \
   CONFIG.PCW_MIO_14_DIRECTION {inout} \
   CONFIG.PCW_MIO_14_IOTYPE {LVCMOS 3.3V} \
   CONFIG.PCW_MIO_14_PULLUP {enabled} \
   CONFIG.PCW_MIO_14_SLEW {slow} \
   CONFIG.PCW_MIO_15_DIRECTION {inout} \
   CONFIG.PCW_MIO_15_IOTYPE {LVCMOS 3.3V} \
   CONFIG.PCW_MIO_15_PULLUP {enabled} \
   CONFIG.PCW_MIO_15_SLEW {slow} \
   CONFIG.PCW_MIO_1_DIRECTION {out} \
   CONFIG.PCW_MIO_1_IOTYPE {LVCMOS 3.3V} \
   CONFIG.PCW_MIO_1_PULLUP {enabled} \
   CONFIG.PCW_MIO_1_SLEW {slow} \
   CONFIG.PCW_MIO_28_DIRECTION {inout} \
   CONFIG.PCW_MIO_28_IOTYPE {LVCMOS 3.3V} \
   CONFIG.PCW_MIO_28_PULLUP {enabled} \
   CONFIG.PCW_MIO_28_SLEW {slow} \
   CONFIG.PCW_MIO_29_DIRECTION {in} \
   CONFIG.PCW_MIO_29_IOTYPE {LVCMOS 3.3V} \
   CONFIG.PCW_MIO_29_PULLUP {enabled} \
   CONFIG.PCW_MIO_29_SLEW {slow} \
   CONFIG.PCW_MIO_2_DIRECTION {inout} \
   CONFIG.PCW_MIO_2_IOTYPE {LVCMOS 3.3V} \
   CONFIG.PCW_MIO_2_PULLUP {disabled} \
   CONFIG.PCW_MIO_2_SLEW {slow} \
   CONFIG.PCW_MIO_30_DIRECTION {out} \
   CONFIG.PCW_MIO_30_IOTYPE {LVCMOS 3.3V} \
   CONFIG.PCW_MIO_30_PULLUP {enabled} \
   CONFIG.PCW_MIO_30_SLEW {slow} \
   CONFIG.PCW_MIO_31_DIRECTION {in} \
   CONFIG.PCW_MIO_31_IOTYPE {LVCMOS 3.3V} \
   CONFIG.PCW_MIO_31_PULLUP {enabled} \
   CONFIG.PCW_MIO_31_SLEW {slow} \
   CONFIG.PCW_MIO_32_DIRECTION {inout} \
   CONFIG.PCW_MIO_32_IOTYPE {LVCMOS 3.3V} \
   CONFIG.PCW_MIO_32_PULLUP {enabled} \
   CONFIG.PCW_MIO_32_SLEW {slow} \
   CONFIG.PCW_MIO_33_DIRECTION {inout} \
   CONFIG.PCW_MIO_33_IOTYPE {LVCMOS 3.3V} \
   CONFIG.PCW_MIO_33_PULLUP {enabled} \
   CONFIG.PCW_MIO_33_SLEW {slow} \
   CONFIG.PCW_MIO_34_DIRECTION {inout} \
   CONFIG.PCW_MIO_34_IOTYPE {LVCMOS 3.3V} \
   CONFIG.PCW_MIO_34_PULLUP {enabled} \
   CONFIG.PCW_MIO_34_SLEW {slow} \
   CONFIG.PCW_MIO_35_DIRECTION {inout} \
   CONFIG.PCW_MIO_35_IOTYPE {LVCMOS 3.3V} \
   CONFIG.PCW_MIO_35_PULLUP {enabled} \
   CONFIG.PCW_MIO_35_SLEW {slow} \
   CONFIG.PCW_MIO_36_DIRECTION {in} \
   CONFIG.PCW_MIO_36_IOTYPE {LVCMOS 3.3V} \
   CONFIG.PCW_MIO_36_PULLUP {enabled} \
   CONFIG.PCW_MIO_36_SLEW {slow} \
   CONFIG.PCW_MIO_37_DIRECTION {inout} \
   CONFIG.PCW_MIO_37_IOTYPE {LVCMOS 3.3V} \
   CONFIG.PCW_MIO_37_PULLUP {enabled} \
   CONFIG.PCW_MIO_37_SLEW {slow} \
   CONFIG.PCW_MIO_38_DIRECTION {inout} \
   CONFIG.PCW_MIO_38_IOTYPE {LVCMOS 3.3V} \
   CONFIG.PCW_MIO_38_PULLUP {enabled} \
   CONFIG.PCW_MIO_38_SLEW {slow} \
   CONFIG.PCW_MIO_39_DIRECTION {inout} \
   CONFIG.PCW_MIO_39_IOTYPE {LVCMOS 3.3V} \
   CONFIG.PCW_MIO_39_PULLUP {enabled} \
   CONFIG.PCW_MIO_39_SLEW {slow} \
   CONFIG.PCW_MIO_3_DIRECTION {inout} \
   CONFIG.PCW_MIO_3_IOTYPE {LVCMOS 3.3V} \
   CONFIG.PCW_MIO_3_PULLUP {disabled} \
   CONFIG.PCW_MIO_3_SLEW {slow} \
   CONFIG.PCW_MIO_48_DIRECTION {out} \
   CONFIG.PCW_MIO_48_IOTYPE {LVCMOS 3.3V} \
   CONFIG.PCW_MIO_48_PULLUP {enabled} \
   CONFIG.PCW_MIO_48_SLEW {slow} \
   CONFIG.PCW_MIO_49_DIRECTION {in} \
   CONFIG.PCW_MIO_49_IOTYPE {LVCMOS 3.3V} \
   CONFIG.PCW_MIO_49_PULLUP {enabled} \
   CONFIG.PCW_MIO_49_SLEW {slow} \
   CONFIG.PCW_MIO_4_DIRECTION {inout} \
   CONFIG.PCW_MIO_4_IOTYPE {LVCMOS 3.3V} \
   CONFIG.PCW_MIO_4_PULLUP {disabled} \
   CONFIG.PCW_MIO_4_SLEW {slow} \
   CONFIG.PCW_MIO_52_DIRECTION {inout} \
   CONFIG.PCW_MIO_52_IOTYPE {LVCMOS 3.3V} \
   CONFIG.PCW_MIO_52_PULLUP {enabled} \
   CONFIG.PCW_MIO_52_SLEW {slow} \
   CONFIG.PCW_MIO_53_DIRECTION {inout} \
   CONFIG.PCW_MIO_53_IOTYPE {LVCMOS 3.3V} \
   CONFIG.PCW_MIO_53_PULLUP {enabled} \
   CONFIG.PCW_MIO_53_SLEW {slow} \
   CONFIG.PCW_MIO_5_DIRECTION {inout} \
   CONFIG.PCW_MIO_5_IOTYPE {LVCMOS 3.3V} \
   CONFIG.PCW_MIO_5_PULLUP {disabled} \
   CONFIG.PCW_MIO_5_SLEW {slow} \
   CONFIG.PCW_MIO_6_DIRECTION {out} \
   CONFIG.PCW_MIO_6_IOTYPE {LVCMOS 3.3V} \
   CONFIG.PCW_MIO_6_PULLUP {disabled} \
   CONFIG.PCW_MIO_6_SLEW {slow} \
   CONFIG.PCW_MIO_7_DIRECTION {out} \
   CONFIG.PCW_MIO_7_IOTYPE {LVCMOS 3.3V} \
   CONFIG.PCW_MIO_7_PULLUP {disabled} \
   CONFIG.PCW_MIO_7_SLEW {slow} \
   CONFIG.PCW_MIO_8_DIRECTION {out} \
   CONFIG.PCW_MIO_8_IOTYPE {LVCMOS 3.3V} \
   CONFIG.PCW_MIO_8_PULLUP {disabled} \
   CONFIG.PCW_MIO_8_SLEW {slow} \
   CONFIG.PCW_MIO_9_DIRECTION {inout} \
   CONFIG.PCW_MIO_9_IOTYPE {LVCMOS 3.3V} \
   CONFIG.PCW_MIO_9_PULLUP {enabled} \
   CONFIG.PCW_MIO_9_SLEW {slow} \
   CONFIG.PCW_MIO_TREE_PERIPHERALS {GPIO#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#USB Reset#Quad SPI Flash#GPIO#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#Unbonded#Unbonded#Unbonded#Unbonded#Unbonded#Unbonded#Unbonded#Unbonded#Unbonded#Unbonded#Unbonded#Unbonded#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#Unbonded#Unbonded#Unbonded#Unbonded#Unbonded#Unbonded#Unbonded#Unbonded#UART 1#UART 1#Unbonded#Unbonded#GPIO#GPIO} \
   CONFIG.PCW_MIO_TREE_SIGNALS {gpio[0]#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]/HOLD_B#qspi0_sclk#reset#qspi_fbclk#gpio[9]#data[0]#cmd#clk#data[1]#data[2]#data[3]#Unbonded#Unbonded#Unbonded#Unbonded#Unbonded#Unbonded#Unbonded#Unbonded#Unbonded#Unbonded#Unbonded#Unbonded#data[4]#dir#stp#nxt#data[0]#data[1]#data[2]#data[3]#clk#data[5]#data[6]#data[7]#Unbonded#Unbonded#Unbonded#Unbonded#Unbonded#Unbonded#Unbonded#Unbonded#tx#rx#Unbonded#Unbonded#gpio[52]#gpio[53]} \
   CONFIG.PCW_NAND_GRP_D8_ENABLE {0} \
   CONFIG.PCW_NAND_PERIPHERAL_ENABLE {0} \
   CONFIG.PCW_NOR_GRP_A25_ENABLE {0} \
   CONFIG.PCW_NOR_GRP_CS0_ENABLE {0} \
   CONFIG.PCW_NOR_GRP_CS1_ENABLE {0} \
   CONFIG.PCW_NOR_GRP_SRAM_CS0_ENABLE {0} \
   CONFIG.PCW_NOR_GRP_SRAM_CS1_ENABLE {0} \
   CONFIG.PCW_NOR_GRP_SRAM_INT_ENABLE {0} \
   CONFIG.PCW_NOR_PERIPHERAL_ENABLE {0} \
   CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0 {7} \
   CONFIG.PCW_QSPI_GRP_FBCLK_ENABLE {1} \
   CONFIG.PCW_QSPI_GRP_FBCLK_IO {MIO 8} \
   CONFIG.PCW_QSPI_GRP_IO1_ENABLE {0} \
   CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE {1} \
   CONFIG.PCW_QSPI_GRP_SINGLE_SS_IO {MIO 1 .. 6} \
   CONFIG.PCW_QSPI_GRP_SS1_ENABLE {0} \
   CONFIG.PCW_QSPI_PERIPHERAL_DIVISOR0 {7} \
   CONFIG.PCW_QSPI_PERIPHERAL_ENABLE {1} \
   CONFIG.PCW_QSPI_PERIPHERAL_FREQMHZ {200} \
   CONFIG.PCW_QSPI_QSPI_IO {MIO 1 .. 6} \
   CONFIG.PCW_SD1_GRP_CD_ENABLE {0} \
   CONFIG.PCW_SD1_GRP_POW_ENABLE {0} \
   CONFIG.PCW_SD1_GRP_WP_ENABLE {0} \
   CONFIG.PCW_SD1_PERIPHERAL_ENABLE {1} \
   CONFIG.PCW_SD1_SD1_IO {MIO 10 .. 15} \
   CONFIG.PCW_SDIO_PERIPHERAL_DIVISOR0 {56} \
   CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ {25} \
   CONFIG.PCW_SDIO_PERIPHERAL_VALID {1} \
   CONFIG.PCW_SINGLE_QSPI_DATA_MODE {x4} \
   CONFIG.PCW_SMC_PERIPHERAL_DIVISOR0 {1} \
   CONFIG.PCW_SPI_PERIPHERAL_DIVISOR0 {1} \
   CONFIG.PCW_TPIU_PERIPHERAL_DIVISOR0 {1} \
   CONFIG.PCW_UART1_GRP_FULL_ENABLE {0} \
   CONFIG.PCW_UART1_PERIPHERAL_ENABLE {1} \
   CONFIG.PCW_UART1_UART1_IO {MIO 48 .. 49} \
   CONFIG.PCW_UART_PERIPHERAL_DIVISOR0 {14} \
   CONFIG.PCW_UART_PERIPHERAL_FREQMHZ {100} \
   CONFIG.PCW_UART_PERIPHERAL_VALID {1} \
   CONFIG.PCW_UIPARAM_ACT_DDR_FREQ_MHZ {533.333374} \
   CONFIG.PCW_UIPARAM_DDR_BANK_ADDR_COUNT {3} \
   CONFIG.PCW_UIPARAM_DDR_BL {8} \
   CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.234} \
   CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.234} \
   CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2 {0.100} \
   CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3 {0.100} \
   CONFIG.PCW_UIPARAM_DDR_CL {7} \
   CONFIG.PCW_UIPARAM_DDR_COL_ADDR_COUNT {10} \
   CONFIG.PCW_UIPARAM_DDR_CWL {6} \
   CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY {4096 MBits} \
   CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {0.054} \
   CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {0.054} \
   CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH {16 Bits} \
   CONFIG.PCW_UIPARAM_DDR_MEMORY_TYPE {DDR 3 (Low Voltage)} \
   CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41K256M16 RE-125} \
   CONFIG.PCW_UIPARAM_DDR_ROW_ADDR_COUNT {15} \
   CONFIG.PCW_UIPARAM_DDR_SPEED_BIN {DDR3_1066F} \
   CONFIG.PCW_UIPARAM_DDR_T_FAW {40.0} \
   CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN {35.0} \
   CONFIG.PCW_UIPARAM_DDR_T_RC {48.75} \
   CONFIG.PCW_UIPARAM_DDR_T_RCD {7} \
   CONFIG.PCW_UIPARAM_DDR_T_RP {7} \
   CONFIG.PCW_USB0_PERIPHERAL_ENABLE {1} \
   CONFIG.PCW_USB0_PERIPHERAL_FREQMHZ {60} \
   CONFIG.PCW_USB0_RESET_ENABLE {1} \
   CONFIG.PCW_USB0_RESET_IO {MIO 7} \
   CONFIG.PCW_USB0_USB0_IO {MIO 28 .. 39} \
   CONFIG.PCW_USB1_RESET_ENABLE {0} \
   CONFIG.PCW_USB_RESET_ENABLE {1} \
   CONFIG.PCW_USB_RESET_SELECT {Share reset pin} \
   CONFIG.PCW_USE_M_AXI_GP0 {0} \
 ] $processing_system7_0


  # Create interface connections
  connect_bd_intf_net -intf_net processing_system7_0_DDR [get_bd_intf_ports DDR] [get_bd_intf_pins processing_system7_0/DDR]
  connect_bd_intf_net -intf_net processing_system7_0_FIXED_IO [get_bd_intf_ports FIXED_IO] [get_bd_intf_pins processing_system7_0/FIXED_IO]


  # Create port connections


  # Create address segments




  # Restore current instance
  current_bd_instance $oldCurInst


  save_bd_design
common::send_msg_id "BD_TCL-1000" "WARNING" "This Tcl script was generated from a block design that has not been validated. It is possible that design <$design_name> may result in errors during validation."


  close_bd_design $design_name 
}
# End of cr_bd_Z_system()
cr_bd_Z_system ""
set_property GENERATE_SYNTH_CHECKPOINT "0" [get_files Z_system.bd ] 


# Create 'synth_1' run (if not found)
if {[string equal [get_runs -quiet synth_1] ""]} {
    create_run -name synth_1 -part xc7z007sclg225-1 -flow {Vivado Synthesis 2017} -strategy "Vivado Synthesis Defaults" -report_strategy {No Reports} -constrset constrs_1
} else {
  set_property strategy "Vivado Synthesis Defaults" [get_runs synth_1]
  set_property flow "Vivado Synthesis 2017" [get_runs synth_1]
}
set obj [get_runs synth_1]
set_property set_report_strategy_name 1 $obj
set_property report_strategy {Vivado Synthesis Default Reports} $obj
set_property set_report_strategy_name 0 $obj
# Create 'synth_1_synth_report_utilization_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0] "" ] } {
  create_report_config -report_name synth_1_synth_report_utilization_0 -report_type report_utilization:1.0 -steps synth_design -runs synth_1
}
set obj [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0]
if { $obj != "" } {


}
set obj [get_runs synth_1]
set_property -name "needs_refresh" -value "1" -objects $obj
set_property -name "part" -value "xc7z007sclg225-1" -objects $obj
set_property -name "strategy" -value "Vivado Synthesis Defaults" -objects $obj


# set the current synth run
current_run -synthesis [get_runs synth_1]


# Create 'impl_1' run (if not found)
if {[string equal [get_runs -quiet impl_1] ""]} {
    create_run -name impl_1 -part xc7z007sclg225-1 -flow {Vivado Implementation 2017} -strategy "Vivado Implementation Defaults" -report_strategy {No Reports} -constrset constrs_1 -parent_run synth_1
} else {
  set_property strategy "Vivado Implementation Defaults" [get_runs impl_1]
  set_property flow "Vivado Implementation 2017" [get_runs impl_1]
}
set obj [get_runs impl_1]
set_property set_report_strategy_name 1 $obj
set_property report_strategy {Vivado Implementation Default Reports} $obj
set_property set_report_strategy_name 0 $obj
# Create 'impl_1_init_report_timing_summary_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0] "" ] } {
  create_report_config -report_name impl_1_init_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps init_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0]
if { $obj != "" } {
set_property -name "is_enabled" -value "0" -objects $obj


}
# Create 'impl_1_opt_report_drc_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0] "" ] } {
  create_report_config -report_name impl_1_opt_report_drc_0 -report_type report_drc:1.0 -steps opt_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0]
if { $obj != "" } {


}
# Create 'impl_1_opt_report_timing_summary_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0] "" ] } {
  create_report_config -report_name impl_1_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps opt_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0]
if { $obj != "" } {
set_property -name "is_enabled" -value "0" -objects $obj


}
# Create 'impl_1_power_opt_report_timing_summary_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0] "" ] } {
  create_report_config -report_name impl_1_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps power_opt_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0]
if { $obj != "" } {
set_property -name "is_enabled" -value "0" -objects $obj


}
# Create 'impl_1_place_report_io_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0] "" ] } {
  create_report_config -report_name impl_1_place_report_io_0 -report_type report_io:1.0 -steps place_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0]
if { $obj != "" } {


}
# Create 'impl_1_place_report_utilization_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0] "" ] } {
  create_report_config -report_name impl_1_place_report_utilization_0 -report_type report_utilization:1.0 -steps place_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0]
if { $obj != "" } {


}
# Create 'impl_1_place_report_control_sets_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0] "" ] } {
  create_report_config -report_name impl_1_place_report_control_sets_0 -report_type report_control_sets:1.0 -steps place_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0]
if { $obj != "" } {


}
# Create 'impl_1_place_report_incremental_reuse_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0] "" ] } {
  create_report_config -report_name impl_1_place_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0]
if { $obj != "" } {
set_property -name "is_enabled" -value "0" -objects $obj


}
# Create 'impl_1_place_report_incremental_reuse_1' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1] "" ] } {
  create_report_config -report_name impl_1_place_report_incremental_reuse_1 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1]
if { $obj != "" } {
set_property -name "is_enabled" -value "0" -objects $obj


}
# Create 'impl_1_place_report_timing_summary_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0] "" ] } {
  create_report_config -report_name impl_1_place_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps place_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0]
if { $obj != "" } {
set_property -name "is_enabled" -value "0" -objects $obj


}
# Create 'impl_1_post_place_power_opt_report_timing_summary_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0] "" ] } {
  create_report_config -report_name impl_1_post_place_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_place_power_opt_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0]
if { $obj != "" } {
set_property -name "is_enabled" -value "0" -objects $obj


}
# Create 'impl_1_phys_opt_report_timing_summary_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0] "" ] } {
  create_report_config -report_name impl_1_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps phys_opt_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0]
if { $obj != "" } {
set_property -name "is_enabled" -value "0" -objects $obj


}
# Create 'impl_1_route_report_drc_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0] "" ] } {
  create_report_config -report_name impl_1_route_report_drc_0 -report_type report_drc:1.0 -steps route_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0]
if { $obj != "" } {


}
# Create 'impl_1_route_report_methodology_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0] "" ] } {
  create_report_config -report_name impl_1_route_report_methodology_0 -report_type report_methodology:1.0 -steps route_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0]
if { $obj != "" } {


}
# Create 'impl_1_route_report_power_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0] "" ] } {
  create_report_config -report_name impl_1_route_report_power_0 -report_type report_power:1.0 -steps route_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0]
if { $obj != "" } {


}
# Create 'impl_1_route_report_route_status_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0] "" ] } {
  create_report_config -report_name impl_1_route_report_route_status_0 -report_type report_route_status:1.0 -steps route_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0]
if { $obj != "" } {


}
# Create 'impl_1_route_report_timing_summary_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0] "" ] } {
  create_report_config -report_name impl_1_route_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps route_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0]
if { $obj != "" } {


}
# Create 'impl_1_route_report_incremental_reuse_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0] "" ] } {
  create_report_config -report_name impl_1_route_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps route_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0]
if { $obj != "" } {


}
# Create 'impl_1_route_report_clock_utilization_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0] "" ] } {
  create_report_config -report_name impl_1_route_report_clock_utilization_0 -report_type report_clock_utilization:1.0 -steps route_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0]
if { $obj != "" } {


}
# Create 'impl_1_post_route_phys_opt_report_timing_summary_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0] "" ] } {
  create_report_config -report_name impl_1_post_route_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_route_phys_opt_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0]
if { $obj != "" } {


}
set obj [get_runs impl_1]
set_property -name "part" -value "xc7z007sclg225-1" -objects $obj
set_property -name "strategy" -value "Vivado Implementation Defaults" -objects $obj
set_property -name "steps.write_bitstream.args.readback_file" -value "0" -objects $obj
set_property -name "steps.write_bitstream.args.verbose" -value "0" -objects $obj


# set the current impl run
current_run -implementation [get_runs impl_1]


puts "INFO: Project created:$project_name"

 

Lab 5 adds a "Block Ram" interface to the FPGA.

 

I never knew what Block Ram was before this project. The intro video gives a bit of intro; but I turned to Dr. Google. and found this video explaining it a little bit more. Yes - I know that this video uses Lattice and not Xilinx; but this is what came up in my search history. Xilinx - time to come up with some more videos and some SEO

 

 

Block Ram is essentially virtual ram within the FPGA. Since an FPGA can be made into "anything", this is one of the options. BRAM can be useful for creating fixed RAM within a program or for crossing clock domains. It uses FIFO, so one clock domain writes in one side, and a different device / clock domain can read from the other. It can buffer data going between the PS (ARM Cortex) and PL (raw FPGA).

 

In doing this lab, I also came across two good videos from EEVBlog. One explaining FPGAs and one talking about the JTAG interface. I had only ever used JTAG to do program chips before; but never knew how much else they are capable of. One very interesting thing was the "boundary scan" capability. It can essentially hijack the physical pins at the last layer before the physical (if we were to use the OSI model). You can use your computer to see the current status of all the 100's of pins on the chips, and even across multiple chips if they are all on the same bus on a given board. You can then "force" any pin to be high or low to check functionality. This was created to alleviate some need for 'bed of nails' testing when chips like FPGAs got more popular and pin counts got to ridiculous amounts that precluded efficient testing with other methods.

 

 

 

Lab 6 is all about Direct Memory Access - DMA.

DMA is a much more efficient way to access memory. This can be handled by the core FPGA and doesn't wast precious CPU cycles like it may otherwise require. Direct memroy access doesn't require all the data to flow through the central processor; but rather through the central interconnect on the chip to the DDR controller, then back and into the RAM.

 

The "slow" data path; as shown in the Avnet training slides.

 

 

Then, with the use of Direct Memory Access, the data flows through the central interconnect to the DMA Controller, then right over to the DDR.

 

The Zync chip has 8 concurrent DDR channels - 4x for the PL and 4x for the PS. Additionally, USB, Gigabit Ethernet, and STIO have intrinsic DMA built in.

 

In the lab, we import the hardware settings from an earlier lab, then export our VHDL and launch the SDK. Within the SDK, we generate a new board support package with the new hardware description, then import a sample program which tests the different methods of moving data. The program calculates the time delta (measured in clock cycles) for the two methods of transfer.

 

-- Simple DMA Design Example --
Above message printing took 2442 clock cycles
Enter number of words you want to transfer:
1=256; 2=512; 3=1024; 4=2048; 5=4096; 6=8192;
Sending 256 bytes


Enter 1 for BRAM to BRAM transfer
Enter 2 for BRAM to DDR3 transfer
Enter 3 for DDR3 to DDR3 transfer
Enter 4 to exit
DDR3 to DDR3 transfer
Moving data through processor took 2249 clock cycles
Setting up interrupt system
Moving data through DMA in Interrupt mode took 1400 clock cycles
Transfer complete
Transfered data verified
Improvement using Interrupt DMA =  1x improvement
-------------------------------------------------------------------


Enter number of words you want to transfer:
1=256; 2=512; 3=1024; 4=2048; 5=4096; 6=8192;
Sending 256 bytes


Enter 1 for BRAM to BRAM transfer
Enter 2 for BRAM to DDR3 transfer
Enter 3 for DDR3 to DDR3 transfer
Enter 4 to exit
DDR3 to DDR3 transfer
Moving data through processor took 2239 clock cycles
Setting up interrupt system
Moving data through DMA in Interrupt mode took 1075 clock cycles
Transfer complete
Transfered data verified
Improvement using Interrupt DMA =  2x improvement
-------------------------------------------------------------------


Enter number of words you want to transfer:
1=256; 2=512; 3=1024; 4=2048; 5=4096; 6=8192;
Sending 8192 bytes


Enter 1 for BRAM to BRAM transfer
Enter 2 for BRAM to DDR3 transfer
Enter 3 for DDR3 to DDR3 transfer
Enter 4 to exit
DDR3 to DDR3 transfer
Moving data through processor took 74035 clock cycles
Setting up interrupt system
Moving data through DMA in Interrupt mode took 22407 clock cycles
Transfer complete
Transfered data verified
Improvement using Interrupt DMA =  3x improvement
-------------------------------------------------------------------


Enter number of words you want to transfer:
1=256; 2=512; 3=1024; 4=2048; 5=4096; 6=8192;
Sending 256 bytes


Enter 1 for BRAM to BRAM transfer
Enter 2 for BRAM to DDR3 transfer
Enter 3 for DDR3 to DDR3 transfer
Enter 4 to exit
DDR3 to DDR3 transfer
Moving data through processor took 2243 clock cycles
Setting up interrupt system
Moving data through DMA in Interrupt mode took 1108 clock cycles
Transfer complete
Transfered data verified
Improvement using Interrupt DMA =  2x improvement
-------------------------------------------------------------------


Enter number of words you want to transfer:
1=256; 2=512; 3=1024; 4=2048; 5=4096; 6=8192;
Sending 256 bytes


Enter 1 for BRAM to BRAM transfer
Enter 2 for BRAM to DDR3 transfer
Enter 3 for DDR3 to DDR3 transfer
Enter 4 to exit
DDR3 to DDR3 transfer
Moving data through processor took 2235 clock cycles
Setting up interrupt system
Moving data through DMA in Interrupt mode took 1085 clock cycles
Transfer complete
Transfered data verified
Improvement using Interrupt DMA =  2x improvement
-------------------------------------------------------------------


Enter number of words you want to transfer:
1=256; 2=512; 3=1024; 4=2048; 5=4096; 6=8192;
Sending 256 bytes


Enter 1 for BRAM to BRAM transfer
Enter 2 for BRAM to DDR3 transfer
Enter 3 for DDR3 to DDR3 transfer
Enter 4 to exit
DDR3 to DDR3 transfer
Moving data through processor took 2236 clock cycles
Setting up interrupt system
Moving data through DMA in Interrupt mode took 1120 clock cycles
Transfer complete
Transfered data verified
Improvement using Interrupt DMA =  1x improvement
-------------------------------------------------------------------


Enter number of words you want to transfer:
1=256; 2=512; 3=1024; 4=2048; 5=4096; 6=8192;
Sending 256 bytes


Enter 1 for BRAM to BRAM transfer
Enter 2 for BRAM to DDR3 transfer
Enter 3 for DDR3 to DDR3 transfer
Enter 4 to exit
DDR3 to DDR3 transfer
Moving data through processor took 2236 clock cycles
Setting up interrupt system
Moving data through DMA in Interrupt mode took 1089 clock cycles
Transfer complete
Transfered data verified
Improvement using Interrupt DMA =  2x improvement
-------------------------------------------------------------------


Enter number of words you want to transfer:
1=256; 2=512; 3=1024; 4=2048; 5=4096; 6=8192;
Sending 256 bytes


Enter 1 for BRAM to BRAM transfer
Enter 2 for BRAM to DDR3 transfer
Enter 3 for DDR3 to DDR3 transfer
Enter 4 to exit
DDR3 to DDR3 transfer
Moving data through processor took 2235 clock cycles
Setting up interrupt system
Moving data through DMA in Interrupt mode took 1167 clock cycles
Transfer complete
Transfered data verified
Improvement using Interrupt DMA =  1x improvement
-------------------------------------------------------------------


Enter number of words you want to transfer:
1=256; 2=512; 3=1024; 4=2048; 5=4096; 6=8192;
Sending 256 bytes


Enter 1 for BRAM to BRAM transfer
Enter 2 for BRAM to DDR3 transfer
Enter 3 for DDR3 to DDR3 transfer
Enter 4 to exit
DDR3 to DDR3 transfer
Moving data through processor took 2235 clock cycles
Setting up interrupt system
Moving data through DMA in Interrupt mode took 1086 clock cycles
Transfer complete
Transfered data verified
Improvement using Interrupt DMA =  2x improvement
-------------------------------------------------------------------


Enter number of words you want to transfer:
1=256; 2=512; 3=1024; 4=2048; 5=4096; 6=8192;
Sending 256 bytes


Enter 1 for BRAM to BRAM transfer
Enter 2 for BRAM to DDR3 transfer
Enter 3 for DDR3 to DDR3 transfer
Enter 4 to exit
DDR3 to DDR3 transfer
Moving data through processor took 2236 clock cycles
Setting up interrupt system
Moving data through DMA in Interrupt mode took 1083 clock cycles
Transfer complete
Transfered data verified
Improvement using Interrupt DMA =  2x improvement
-------------------------------------------------------------------


Enter number of words you want to transfer:
1=256; 2=512; 3=1024; 4=2048; 5=4096; 6=8192;
Sending 256 bytes


Enter 1 for BRAM to BRAM transfer
Enter 2 for BRAM to DDR3 transfer
Enter 3 for DDR3 to DDR3 transfer
Enter 4 to exit
DDR3 to DDR3 transfer
Moving data through processor took 2231 clock cycles
Setting up interrupt system
Moving data through DMA in Interrupt mode took 1074 clock cycles
Transfer complete
Transfered data verified
Improvement using Interrupt DMA =  2x improvement
-------------------------------------------------------------------


Enter number of words you want to transfer:
1=256; 2=512; 3=1024; 4=2048; 5=4096; 6=8192;
Sending 256 bytes


Enter 1 for BRAM to BRAM transfer
Enter 2 for BRAM to DDR3 transfer
Enter 3 for DDR3 to DDR3 transfer
Enter 4 to exit
DDR3 to DDR3 transfer
Moving data through processor took 2236 clock cycles
Setting up interrupt system
Moving data through DMA in Interrupt mode took 1068 clock cycles
Transfer complete
Transfered data verified
Improvement using Interrupt DMA =  2x improvement
-------------------------------------------------------------------


Enter number of words you want to transfer:
1=256; 2=512; 3=1024; 4=2048; 5=4096; 6=8192;
Sending 256 bytes


Enter 1 for BRAM to BRAM transfer
Enter 2 for BRAM to DDR3 transfer
Enter 3 for DDR3 to DDR3 transfer
Enter 4 to exit
DDR3 to DDR3 transfer
Moving data through processor took 2231 clock cycles
Setting up interrupt system
Moving data through DMA in Interrupt mode took 1188 clock cycles
Transfer complete
Transfered data verified
Improvement using Interrupt DMA =  1x improvement
-------------------------------------------------------------------


Enter number of words you want to transfer:
1=256; 2=512; 3=1024; 4=2048; 5=4096; 6=8192;
Sending 256 bytes


Enter 1 for BRAM to BRAM transfer
Enter 2 for BRAM to DDR3 transfer
Enter 3 for DDR3 to DDR3 transfer
Enter 4 to exit
DDR3 to DDR3 transfer
Moving data through processor took 2235 clock cycles
Setting up interrupt system
Moving data through DMA in Interrupt mode took 1070 clock cycles
Transfer complete
Transfered data verified
Improvement using Interrupt DMA =  2x improvement
-------------------------------------------------------------------


Enter number of words you want to transfer:
1=256; 2=512; 3=1024; 4=2048; 5=4096; 6=8192;
Sending 256 bytes


Enter 1 for BRAM to BRAM transfer
Enter 2 for BRAM to DDR3 transfer
Enter 3 for DDR3 to DDR3 transfer
Enter 4 to exit
DDR3 to DDR3 transfer
Moving data through processor took 2231 clock cycles
Setting up interrupt system
Moving data through DMA in Interrupt mode took 1097 clock cycles
Transfer complete
Transfered data verified
Improvement using Interrupt DMA =  2x improvement
-------------------------------------------------------------------


Enter number of words you want to transfer:
1=256; 2=512; 3=1024; 4=2048; 5=4096; 6=8192;
Sending 256 bytes


Enter 1 for BRAM to BRAM transfer
Enter 2 for BRAM to DDR3 transfer
Enter 3 for DDR3 to DDR3 transfer
Enter 4 to exit
DDR3 to DDR3 transfer
Moving data through processor took 2235 clock cycles
Setting up interrupt system
Moving data through DMA in Interrupt mode took 1079 clock cycles
Transfer complete
Transfered data verified
Improvement using Interrupt DMA =  2x improvement
-------------------------------------------------------------------


Enter number of words you want to transfer:
1=256; 2=512; 3=1024; 4=2048; 5=4096; 6=8192;
Sending 256 bytes


Enter 1 for BRAM to BRAM transfer
Enter 2 for BRAM to DDR3 transfer
Enter 3 for DDR3 to DDR3 transfer
Enter 4 to exit
DDR3 to DDR3 transfer
Moving data through processor took 2231 clock cycles
Setting up interrupt system
Moving data through DMA in Interrupt mode took 1146 clock cycles
Transfer complete
Transfered data verified
Improvement using Interrupt DMA =  1x improvement
-------------------------------------------------------------------


Enter number of words you want to transfer:
1=256; 2=512; 3=1024; 4=2048; 5=4096; 6=8192;
Sending 256 bytes


Enter 1 for BRAM to BRAM transfer
Enter 2 for BRAM to DDR3 transfer
Enter 3 for DDR3 to DDR3 transfer
Enter 4 to exit
DDR3 to DDR3 transfer
Moving data through processor took 2236 clock cycles
Setting up interrupt system
Moving data through DMA in Interrupt mode took 1080 clock cycles
Transfer complete
Transfered data verified
Improvement using Interrupt DMA =  2x improvement
-------------------------------------------------------------------


Enter number of words you want to transfer:
1=256; 2=512; 3=1024; 4=2048; 5=4096; 6=8192;
Sending 256 bytes


Enter 1 for BRAM to BRAM transfer
Enter 2 for BRAM to DDR3 transfer
Enter 3 for DDR3 to DDR3 transfer
Enter 4 to exit
DDR3 to DDR3 transfer
Moving data through processor took 2278 clock cycles
Setting up interrupt system
Moving data through DMA in Interrupt mode took 1122 clock cycles
Transfer complete
Transfered data verified
Improvement using Interrupt DMA =  2x improvement
-------------------------------------------------------------------


Enter number of words you want to transfer:
1=256; 2=512; 3=1024; 4=2048; 5=4096; 6=8192;
Sending 256 bytes


Enter 1 for BRAM to BRAM transfer
Enter 2 for BRAM to DDR3 transfer
Enter 3 for DDR3 to DDR3 transfer
Enter 4 to exit
DDR3 to DDR3 transfer
Moving data through processor took 2236 clock cycles
Setting up interrupt system
Moving data through DMA in Interrupt mode took 1083 clock cycles
Transfer complete
Transfered data verified
Improvement using Interrupt DMA =  2x improvement
-------------------------------------------------------------------


Enter number of words you want to transfer:
1=256; 2=512; 3=1024; 4=2048; 5=4096; 6=8192;
Sending 256 bytes


Enter 1 for BRAM to BRAM transfer
Enter 2 for BRAM to DDR3 transfer
Enter 3 for DDR3 to DDR3 transfer
Enter 4 to exit
DDR3 to DDR3 transfer
Moving data through processor took 2236 clock cycles
Setting up interrupt system
Moving data through DMA in Interrupt mode took 1114 clock cycles
Transfer complete
Transfered data verified
Improvement using Interrupt DMA =  2x improvement
-------------------------------------------------------------------


Enter number of words you want to transfer:
1=256; 2=512; 3=1024; 4=2048; 5=4096; 6=8192;
Sending 256 bytes


Enter 1 for BRAM to BRAM transfer
Enter 2 for BRAM to DDR3 transfer
Enter 3 for DDR3 to DDR3 transfer
Enter 4 to exit
DDR3 to DDR3 transfer
Moving data through processor took 2236 clock cycles
Setting up interrupt system
Moving data through DMA in Interrupt mode took 1084 clock cycles
Transfer complete
Transfered data verified
Improvement using Interrupt DMA =  2x improvement
-------------------------------------------------------------------


Enter number of words you want to transfer:
1=256; 2=512; 3=1024; 4=2048; 5=4096; 6=8192;
Sending 256 bytes


Enter 1 for BRAM to BRAM transfer
Enter 2 for BRAM to DDR3 transfer
Enter 3 for DDR3 to DDR3 transfer
Enter 4 to exit
DDR3 to DDR3 transfer
Moving data through processor took 2236 clock cycles
Setting up interrupt system
Moving data through DMA in Interrupt mode took 1140 clock cycles
Transfer complete
Transfered data verified
Improvement using Interrupt DMA =  1x improvement
-------------------------------------------------------------------


Enter number of words you want to transfer:
1=256; 2=512; 3=1024; 4=2048; 5=4096; 6=8192;
Sending 256 bytes


Enter 1 for BRAM to BRAM transfer
Enter 2 for BRAM to DDR3 transfer
Enter 3 for DDR3 to DDR3 transfer
Enter 4 to exit
DDR3 to DDR3 transfer
Moving data through processor took 2236 clock cycles
Setting up interrupt system
Moving data through DMA in Interrupt mode took 1073 clock cycles
Transfer complete
Transfered data verified
Improvement using Interrupt DMA =  2x improvement
-------------------------------------------------------------------


Enter number of words you want to transfer:
1=256; 2=512; 3=1024; 4=2048; 5=4096; 6=8192;
Sending 256 bytes


Enter 1 for BRAM to BRAM transfer
Enter 2 for BRAM to DDR3 transfer
Enter 3 for DDR3 to DDR3 transfer
Enter 4 to exit
DDR3 to DDR3 transfer
Moving data through processor took 2235 clock cycles
Setting up interrupt system
Moving data through DMA in Interrupt mode took 1086 clock cycles
Transfer complete
Transfered data verified
Improvement using Interrupt DMA =  2x improvement
-------------------------------------------------------------------


Enter number of words you want to transfer:
1=256; 2=512; 3=1024; 4=2048; 5=4096; 6=8192;
Sending 256 bytes


Enter 1 for BRAM to BRAM transfer
Enter 2 for BRAM to DDR3 transfer
Enter 3 for DDR3 to DDR3 transfer
Enter 4 to exit
DDR3 to DDR3 transfer
Moving data through processor took 2231 clock cycles
Setting up interrupt system
Moving data through DMA in Interrupt mode took 1087 clock cycles
Transfer complete
Transfered data verified
Improvement using Interrupt DMA =  2x improvement
-------------------------------------------------------------------


Enter number of words you want to transfer:
1=256; 2=512; 3=1024; 4=2048; 5=4096; 6=8192;
Sending 512 bytes


Enter 1 for BRAM to BRAM transfer
Enter 2 for BRAM to DDR3 transfer
Enter 3 for DDR3 to DDR3 transfer
Enter 4 to exit
DDR3 to DDR3 transfer
Moving data through processor took 4527 clock cycles
Setting up interrupt system
Moving data through DMA in Interrupt mode took 1803 clock cycles
Transfer complete
Transfered data verified
Improvement using Interrupt DMA =  2x improvement
-------------------------------------------------------------------


Enter number of words you want to transfer:
1=256; 2=512; 3=1024; 4=2048; 5=4096; 6=8192;
Sending 8192 bytes


Enter 1 for BRAM to BRAM transfer
Enter 2 for BRAM to DDR3 transfer
Enter 3 for DDR3 to DDR3 transfer
Enter 4 to exit
DDR3 to DDR3 transfer
Moving data through processor took 72551 clock cycles
Setting up interrupt system
Moving data through DMA in Interrupt mode took 22384 clock cycles
Transfer complete
Transfered data verified
Improvement using Interrupt DMA =  3x improvement
-------------------------------------------------------------------


Enter number of words you want to transfer:
1=256; 2=512; 3=1024; 4=2048; 5=4096; 6=8192;
Sending 256 bytes


Enter 1 for BRAM to BRAM transfer
Enter 2 for BRAM to DDR3 transfer
Enter 3 for DDR3 to DDR3 transfer
Enter 4 to exit
BRAM to DDR3 transfer
Moving data through processor took 23107 clock cycles
Setting up interrupt system
Moving data through DMA in Interrupt mode took 1796 clock cycles
Transfer complete
Transfered data verified
Improvement using Interrupt DMA = 12x improvement
-------------------------------------------------------------------


Enter number of words you want to transfer:
1=256; 2=512; 3=1024; 4=2048; 5=4096; 6=8192;
Sending 256 bytes


Enter 1 for BRAM to BRAM transfer
Enter 2 for BRAM to DDR3 transfer
Enter 3 for DDR3 to DDR3 transfer
Enter 4 to exit
DDR3 to DDR3 transfer
Moving data through processor took 2249 clock cycles
Setting up interrupt system
Moving data through DMA in Interrupt mode took 1075 clock cycles
Transfer complete
Transfered data verified
Improvement using Interrupt DMA =  2x improvement
-------------------------------------------------------------------


Enter number of words you want to transfer:
1=256; 2=512; 3=1024; 4=2048; 5=4096; 6=8192;
Sending 256 bytes


Enter 1 for BRAM to BRAM transfer
Enter 2 for BRAM to DDR3 transfer
Enter 3 for DDR3 to DDR3 transfer
Enter 4 to exit
BRAM to DDR3 transfer
Moving data through processor took 23098 clock cycles
Setting up interrupt system
Moving data through DMA in Interrupt mode took 1804 clock cycles
Transfer complete
Transfered data verified
Improvement using Interrupt DMA = 12x improvement
-------------------------------------------------------------------


Enter number of words you want to transfer:
1=256; 2=512; 3=1024; 4=2048; 5=4096; 6=8192;
Sending 256 bytes


Enter 1 for BRAM to BRAM transfer
Enter 2 for BRAM to DDR3 transfer
Enter 3 for DDR3 to DDR3 transfer
Enter 4 to exit
DDR3 to DDR3 transfer
Moving data through processor took 2236 clock cycles
Setting up interrupt system
Moving data through DMA in Interrupt mode took 1138 clock cycles
Transfer complete
Transfered data verified
Improvement using Interrupt DMA =  1x improvement
-------------------------------------------------------------------


Enter number of words you want to transfer:
1=256; 2=512; 3=1024; 4=2048; 5=4096; 6=8192;
Sending 1024 bytes


Enter 1 for BRAM to BRAM transfer
Enter 2 for BRAM to DDR3 transfer
Enter 3 for DDR3 to DDR3 transfer
Enter 4 to exit
DDR3 to DDR3 transfer
Moving data through processor took 8854 clock cycles
Setting up interrupt system
Moving data through DMA in Interrupt mode took 3141 clock cycles
Transfer complete
Transfered data verified
Improvement using Interrupt DMA =  2x improvement
-------------------------------------------------------------------


Enter number of words you want to transfer:
1=256; 2=512; 3=1024; 4=2048; 5=4096; 6=8192;
Sending 256 bytes


Enter 1 for BRAM to BRAM transfer
Enter 2 for BRAM to DDR3 transfer
Enter 3 for DDR3 to DDR3 transfer
Enter 4 to exit
DDR3 to DDR3 transfer
Moving data through processor took 2236 clock cycles
Setting up interrupt system
Moving data through DMA in Interrupt mode took 1071 clock cycles
Transfer complete
Transfered data verified
Improvement using Interrupt DMA =  2x improvement
-------------------------------------------------------------------


Enter number of words you want to transfer:
1=256; 2=512; 3=1024; 4=2048; 5=4096; 6=8192;
Sending 512 bytes


Enter 1 for BRAM to BRAM transfer
Enter 2 for BRAM to DDR3 transfer
Enter 3 for DDR3 to DDR3 transfer
Enter 4 to exit
DDR3 to DDR3 transfer
-- Exiting main() --

 

 

The most interesting one was BRAM to DDR 3 transfer of 256 bytes. Moving the data via the processor took 23,098 clock cycles; but using the DMAC, it only took 1804 clock cycles! An astounding increase in performance! (See below excerpt)

 

 

Enter number of words you want to transfer:
1=256; 2=512; 3=1024; 4=2048; 5=4096; 6=8192;
Sending 256 bytes


Enter 1 for BRAM to BRAM transfer
Enter 2 for BRAM to DDR3 transfer
Enter 3 for DDR3 to DDR3 transfer
Enter 4 to exit
BRAM to DDR3 transfer
Moving data through processor took 23098 clock cycles
Setting up interrupt system
Moving data through DMA in Interrupt mode took 1804 clock cycles
Transfer complete
Transfered data verified
Improvement using Interrupt DMA = 12x improvement
-------------------------------------------------------------------

 

 

 

The conclusion of these last three labs - I can see a lot more as to why FPGAs are considered so advanced. Their very core design allows them to be flexible and to do many, many different things. And along with that comes the requirement of knowing what exactly one is doing. "With great power comes great responsibility". I can see that this course seems designed for true full-time embedded programmers who need to know the exact inner workings and the nuts and bolts of how to make their program run efficiently. I am again very thankful to Element 15 and Xilinx for putting this training together!

 

Hoping to finish the remaining three labs in the next week or so; and hopefully I am able to get some videos of what I've been learning