So far this has been the most challenging lab, mostly because of the amount of typing. We added a PWM module with an interrupt. If you've been following along, you'll see that during this lab we added the portion outlined in red.
So we added the PWM module that we created, a Logic Analyzer from the built in IP, and a JTAG interface, also from the built in IP.
As you start to go through the process of creating the new IP, you are asked a few questions, and ultimately a new instance of the Vivado tool is opened.
This is a Block Diagram of what will be created:
A basic VHDL file is created for you and at this point there are instructions to go in and edit these files.
So, as a Path to Programmable, teaching you how to use VHDL/HDL, I think it's a little short. There is not much of an explanation about what you are adding, and there are times that you will type in everything they give you, the editor will indicate that there is a syntax error, you go through and double and triple check that everything you typed is correct, only to find out that they will fill in the rest of the block later, and then the errors clear up.
There are several more blocks similar to the above, where you are just typing in the editor.
Once you have completed the data entry, you are then able to synthesize the design. Once that is complete, you can package your custom IP, which involves reviewing a bunch of settings:
Essentially you need to make all the checkmarks green. Once that is complete, you close and save the project, then you are able to use the newly created IP in your main project.
That process was pretty straightforward and was reminiscent of the steps we followed earlier to add the BRAM.
This was the most time intensive lab so far, and probably the most complicated. There was a lot of typing, without much explanation. The other interesting thing was that at no time during this lab did I plug in the Mini Zed board.
I think the next lab will involve using the IP that we created to blink an LED, and perhaps to monitor for the interrupt that we created. The future lab will also hopefully reveal why we needed the JTAG interface as well as the logic analyzer.
Until then ....