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I spent the weekend figuring out Lab 9.  It turns out that my file system wasn't in line with the TCL script.  The instructions are as follows: ***NOTE*** If you receive an error running the Tcl command above please delete your entire ZynqDesign project and ip repo. Then start from Experiment 1 step 1 in which you unzip a pre-built lab 8 project and ip repo to the correct location. The reason you received an error was most likely due to an incorrect naming convention that was done in ...
I have finished Lab 7! This one was quite a bit longer for me and took three or four nights to get through.   About:Through Avnet, Xilinx and Element14, a training program to learn about the Zynq 7000 platform which is System On Chip combining an FPGA with an ARM processor. This comes to the students as complete development board packed with goodies like a wireless chip from MuRata (BT/BTLE/WIFI), 8GB Flash memory, onboard RAM, USB to JTAG (JTAG programmable over USB), Arduino-style headers ...