All my previous blogs can be read in detail here Path to Programmable  This blog is further continued from Week 4: Done!! Lab 7 A good read of the previous blog 7 is necessary to understand this Lab 8 as they are related in the project context.

 

 

Lab 8 Overview and Objectives

 

Often times when hardware engineers create new IP they want to test it, not only through simulation but also in hardware. But with embedded designs like Zynq, it requires software to be written to test the IP. In Vivado 2014.3 Xilinx has introduced a new LogiCORE™ IP JTAG-AXI core, which we added in the last lab. This core is a customizable core that can generate AXI transactions and drive AXI signals internal to the AP SoC at run-time. We’ll use this core to test our IP. To run the JTAG-AXI core, we’ll utilize Vivado Logic Analyzer. Lastly, we’ll add a pre-built software application to validate our test. The software application will include an Interrupt Service Routine (ISR) that processes interrupts from our custom IP.

 

When you have completed Lab 8, you will know how to do the following:

 

• Perform run-time interactions with IP cores

• Run software that handles PL-generated interrupts and utilizes an Interrupt Service Routine.

 

Experiment 1: Testing the software that handles PL-generated interrupts and utilizes an Interrupt Service Routine

 

In this first part of lab 8; the previously created applications in lab 6 are imported with software files such as BRAM; Memory tester; peripheral test and a new application in software was added called LED Dimmer. This led dimmer application is created using the standalone bsp as shown below. The software C source files for LED dimmer were given to us in the support documents which I integrated in the project. Here then I learnt about the ISR (PWMIsr) and Interrupt System (SetupInterruptSystem) functions.

 

Creating workspace for lab8

 

 

Ready to import the C files from lab 6

 

Imported all the software files such as BRAM; Memory tester; peripheral test

 

 

Added the LED Dimmer ISR routine to the Lab8 project and ready to test the led dimming code.

 

The Test Results for LED dimmer control at PL LED via software in SDK

 

 

 

The final control of the results.

 

Experiment 2: Vivado Hardware Analyzer

 

The ILA core is alternate to the chipscope which many have used in ISE. The ILA feature is integrated in Vivado and not stand-alone as it used to be for chipscope before. I really like this feature as it is quite handy is debugging the hardware signals and finding first unknown issues in a custom design.

 

What is ILA core?

 

The customizable Integrated Logic Analyzer (ILA) IP core is a logic analyzer core that can be used to monitor the internal signals of a design. The ILA core includes many advanced features of modern logic analyzers, including Boolean trigger equations, and edge transition triggers. Because the ILA core is synchronous to the design being monitored, all design clock constraints that are applied to your design are also applied to the components inside the ILA core.

 

More info can be read here on the ILA core https://www.xilinx.com/support/documentation/ip_documentation/ila/v6_1/pg172-ila.pdf

 

This experiment shows how to open and setup the Vivado Hardware Analyzer. We’ll capture hardware events and trigger on exceptions to validate the hardware design.

 

{gallery} Vivado Hardware Analyzer

ILA Vivado Hardware Analyzer

ILA Vivado Hardware Analyzer Properties

ILA Vivado Hardware Analyzer

ILA Vivado Hardware Analyzer

ILA Vivado Hardware Analyzer

 

 

 

{gallery} My Customized Tests in ILA Vivado Hardware Analyzer

Customizing Tests in ILA Vivado Hardware Analyzer

Customizing Tests in ILA Vivado Hardware Analyzer

Playing and Customizing Tests in ILA Vivado Hardware Analyzer

The new modified vivado project with the Customizes IP

The new vivado project with the Customizes IP

 

 

Experiment 3: Run-time Interactions with the AXI

 

Again, it’s often very likely that hardware engineers will not have software code available when they are ready to test their IP. For this reason, Xilinx has created the LogiCORE™ IP JTAG-AXI core. This experiment shows how to interact with the JTAG-AXI core. We’ll perform AXI transactions through the AXI JTAG Master via TCL commands to perform run-time interactions to test the IP cores. Currently the software is running from the PS and sending commands to our peripherals through the AXI Interconnect.

 

Playing with the hardware final design and looking into signal flows between the ip cores

 

Using tcl scripting to write to the ILA core.

 

 

Adding parameters to the ILA core via TCL scripts to test the built hardware

 

Experiment 4: Delivering Hardware to the Software Team

 

The previous experiment showed how to interact with the JTAG-AXI core to test the IP outside of a software environment. Now that the hardware platform development is complete and we have tested the hardware platform to validate that it functions as expected, we will perform some clean up step. Since the JTAG-AXI core is not something that software engineers would need in order to develop software, it will be removed during this experiment. One might say the same thing of the ILA core, however we will remove that in lab 9.

 

 

Conclusion

In this lab the main focus was on learning the debugging tool available in Vivado and Vivado SDK. Indeed they were very handy to learn and very much needed to reduce the headache of the programmers and hardware engineers. I did spend quite sometime learning to use the ILA core and get into debugging the design.