HW Chapter 2 video: Xilinx Embedded Tool Flow

The presenter first went over the different Vivado Design Suite editions: WebPACK is free and supports the common Zynq devices that are found on most development boards (7010 and 7020), and the more expensive HL System & Design editions which support additional features like Partial Reconfiguration & System Generator for DSP.

The next slide summarized the typical workflow of Zynq Development. The hardware designer uses Vivado, the IP Integrator etc. for programming the PL (Programmable Logic), while the software designer uses Xilinx SDK for code that will run on the PS.

The next couple of slides highlighted the advantages of IP based design, which allows users to simply drag and drop pre-designed, tested and packaged IP into their project. This is similar to how typical HDL structural modelling works, except that the IP integrator takes it further by automating many tasks like interconnections and DRC.

To get started with IP based workflow, create a block design in Vivado & click on the '+' button to view available IP.

 

Lab 1 - Building a Basic Zynq Design

 

This lab was pretty simple as the agenda was to create a basic Zynq system.

To start, create a new project in Vivado & select the specific part being used - which is a xc7z007sclg225-1 (Z-7007S single ARM Cortex A9 Zynq with 23K Logic Cells, 225 I/O pins & speed grade 1) on the MiniZed.

Since I had downloaded the board definition files for the MiniZed, I could have also switched to the 'boards' tab and selected the MiniZed directly.

We then create a new block design and add the 'Zynq IP' by clicking on the '+'.

The Zynq Processing System is added to the design, and we run 'Block Automation', which in this case makes the connections for DDR & I/O external:

To customize the Zynq Processing System, double-click on it, which will open up a configuration window.

 

HW Chapter 3 video: Zynq Processor Overview

 

This video focused on the technical aspects of the Zynq-7000 PS: the CPU, peripherals, memory interfaces & the AXI Interconnect.

There were a couple of slides on the memory system of the ARM: L1 & L2 caches, Snoop Control Unit & Accelerator Coherency Port. This was followed by a little about the Cortex-A9 NEON SIMD co-processor, the FPU Engine, clock tree in the Zynq-7000 for the CPU, DDR, I/O & PL and the DDR interface. The DDR controller supports variations of DDR2 & DDR3, a couple of different bus speeds & bus widths (though IIRC the SKU used on the MiniZed is limited to a 16-bit interface).

This video was pretty technical - a little more than it should have been at this point, but it was a nice refresher on computer architecture!

 

Lab 2 - PS Configuration Part 1 - HelloWorld

 

Picking up from where we stopped at the end of Lab 1, it's time to customize the Zynq7 Processing System.

 

{gallery} Zynq PS Configuration

Set the bank voltages to 3.3V

Enable the UART

Set the UART baud rate

Disable 'FCLK_CLK0': This is a clock that is routed to the PL, which we won't be using for now.

Also disable the AXI GPIO Interface since we're not using it.

Change the type of DRAM to DDR3L & select the correct part - this is based on how everything is wired up on the MiniZed

 

After selecting the DDR3L part, enter the timing parameters. The values depend on PCB routing, and pre-calculated values were provided. An Appendix at the end of the chapter also provided an insight into how these values are calculated, and a link to the Technical Reference Manual of the Zynq-7000 for referring to documentation on the DRAM controller.

 

{gallery} DRAM Configuration

Enter the given (pre-calculated) values.

The chapter in the Zynq-7000 TRM that describes the memory controller.

 

Next, validate the design and generate a HDL wrapper.

Click on 'Generate Bitstream', which will automatically elaborate, synthesize & implement the design - which takes around 3 minutes.

This is the result: the Z_system contains the system that we've just configured, and the external connections go to the DDR & I/O. Clicking on the '+' reveals a structural design and after going in a couple of layers deeper you will see something that looks like the screenshot on the right.

Zooming in closer reveals all the connections. This is a very simple design since it only uses the DDR & UART. The PS-PL interconnects haven't been used for now, and the PL is completely programmed. Vivado makes all these connections automatically so that you don't need to break a sweat. The image on the right shows how everything looks like on the chip. The 4 blocks (PL) are empty since the PL hasn't been programmed, and on the left is the ARM core & DDR interface.

Export the hardware, and launch Xilinx SDK.

Create a new BSP & Application. You project will now consist of 3 parts: the C application, Board Support Package & ARM Embedded Hardware.

Since we created the project using a template for 'Hello World' we can run it directly. Create 'Run Configuration' and use the 'Xilinx System Debugger'.

Change the position of the boot switch on the MiniZed to J from F (so that it uses JTAG instead of Flash) and plug it in. Connect to the serial port, and click run.

That's it for Lab 2!

 

The training is certainly better than most Zynq tutorials end up being a list of instructions that need to be followed to do something.  The tutorials don't try to explain everything (which is fine!), but provide adequate reasoning as to why some things are configured. I liked the way that the DRAM configuration was handled - pre-calculated values were provided so that the trainee could plug them in and continue (instead of explaining it right there, which could result in the trainee forgetting where they stopped off), but an Appendix at the end explained how they had been derived, and provided a link to the Technical Reference Manual so that trainees can have a look at the documentation when they feel like it.

 

Progress:

HW Chapter 2 video: Xilinx Embedded Tool Flow

Lab 1 - Building a Basic Zynq Design

HW Chapter 3 video: Zynq Processor Overview

Lab 2 - PS Configuration Part 1 - HelloWorld

 

Next up:

HW Chapter 4 video: Peripherals, Peripherals & more Peripherals!

Lab 3 - PS Configuration Part 2 - MIO Peripherals