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Path to Programmable

December 2018 Next month
Hi Friends , in the Previous post we have Created our own Custom PWM IP in Vivado and just Integrated it in our Design. In this Post we will run it On Minized Board. In the Next Post , I will show the Debugging Routes we will trace : For these functionalities we have added Integrated Logic Analyzer Core and JTAG to AXI master cores in our Block Design , I will Clear how these work in the Next post.   After Creating the Block Design with Our Custom IP added in Design this is no new Task ...
The first few labs in the SW Module are mostly a more in depth look at the SDK product provided with the Vivado Suite.   Lab 0 covers installing all the required tools. All of these steps were completed as part of the first set of labs, so there really wasn't anything to do.   They discuss the fact that the Editor is based on Eclipse IDE.   In Lab 1 they go into depth regarding the file we exported at the end of Lab 9 in the HW module. Z_system_wrapper.hdf. They explain that th ...
  I tried out a couple of things that weren't a part of the Path to Programmable Course Syllabus, but I thought I'd share them: How to setup the clocks for PL-only designs with the MiniZed 3-bit VGA output from the MiniZed without a PMOD.   MiniZed Clocking  As far as trial runs are concerned, running a PL-only design follows the same process as Xilinx's non-SoC parts like the Spartan & Artix: instantiate all HDL source code in a top level wrapper, assign the I/O pins (con ...
In the previous blog post Path to Programmable Blog 5 - Creating Custom IP , we created custom IP which comprised of some HDL code that implemented a PWM controller, which was then connected to the AXI bus as an AXI-4 Lite Slave, allowing the PS to control the PWM controller. We also added an Integrated Logic Analyzer and JTAG-AXI core.   HW Chapter 9 video: Vivado's Hardware Manager This video went over the different debugging techniques: Although the ILA is implemented in the FPGA fabr ...
In Path to Programmable Blog 4 - Adding a PL Peripheral & using PS DMA, we added Block RAM to the PL and connected it to the PS using the AXI interface. We also looked at how we can use DMA to speed up transfers. The Block RAM was added to the PL using Xilinx's IP that is bundled with Vivado - which was automatically configured and connected. When working on custom designs, we need to generate 'IP' of our own i.e. somehow link registers/datapaths in our HDL to the AXI interface so that th ...
About:Through Avnet, Xilinx and Element14, a training program to learn about the Zynq 7000 platform which is System On Chip combining an FPGA with an ARM processor. This comes to the students as complete development board packed with goodies like a wireless chip from MuRata (BT/BTLE/WIFI), 8GB Flash memory, onboard RAM, USB to JTAG (JTAG programmable over USB), Arduino-style headers (3.3V compatible only), Microphone, Bi-Color LED, and two additional expansion ports.   See all blog posts fo ...
You may remember when we left off, we removed the JTAG interface from our board design, but we left the PWM module and the Logic Analyzer, so the Block Design looked like this:     and I said something about next lab we would do some more TCL scripting and I guessed it would be about removing some IP that we added. BOY WAS I EVER WRONG.   They had us open Vivado, go to the TCL console, change directories into the support directory for lab 9 and type:   source ./lab9.tcl ...
In the preceding posts, we had a quick look at what Zynq-7000 is (Path to Programmable Blog 1 - Getting Started), the workflow (Path to Programmable Blog 2 - Xilinx Tool Flow & Getting Started with Zynq-7000) and we configured a couple of PS peripherals and ran tests (Path to Programmable Blog 3 - PS Peripheral Configuration & TCL). Now comes the important part: making the PL talk to the PS & DRAM, which will be used in probably every design that targets Zynq.   HW Chapter 6 vi ...
Path to Programmable Blog 2 - Xilinx Tool Flow & Getting Started with Zynq-7000 was an introduction to typical Zynq workflow: first configure the hardware (PS & PL) in Vivado, and then export it to Xilinx SDK to work on the software side of things. This blog post covers the next 2 sets of videos & labs: the first set covers PS peripheral configuration & the second one is a quick look at using TCL in Vivado. HW Chapter 4 video: Peripherals, Peripherals & more Peripherals! This ...