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Hello,   In this lesson, we create our own application; and explore some of the available code examples for the Zynq MiniZed training board.   About:Through Avnet, Xilinx and Element14, a training program to learn about the Zynq 7000 platform which is System On Chip combining an FPGA with an ARM processor. This comes to the students as complete development board packed with goodies like a wireless chip from MuRata (BT/BTLE/WIFI), 8GB Flash memory, onboard RAM, USB to JTAG (JTAG progra ...
Lab 3 - Board Support Package Welcome back everyone - hope you all have a great new year! This lab goes into much more detail about what the Board Support Package (BSP) is and does when it comes to the software SDK. For me, this cleared up a lot of questions I had regarding it and why we have to generate it from the HDL (Hardware description) that Vivado outputs. Read on to find out more!   About:Through Avnet, Xilinx and Element14, a training program to learn about the Zynq 7000 platform w ...
Chapter 10 Video - Xilinx Libraries  This video explored the system libraries that Xilinx includes with SDK. These can be configured and initialized from the BSP settings eg- the Flash library allows users to select the manufacturer (Atmel, Microchip, Micron etc.) and the different interfaces. Xilinx libraries also comes bundled with example code. Lab 10 - Xilinx Libraries  In this lab, the flash library was used to read & write configuration data - which in this particular c ...
The Module 2 of the MiniZed Path to Programmable is focused on software development in xilinx fpga. After viewing the training videos; this module is about Vivado SDK and SDK Application development flow. The previous minized hardware development ZYNQ blogs can be read here Summary of Module 1 Path to Programmable ZYNQ HW blogs The Software related blogs are here Summary of Module 2 Path to Programmable ZYNQ SW blogs   After generating the zynq HW the board support packages from the HW p ...
The list of the step by step zynq hardware development blog learnings and projects are as below   Topics in the Minized Zynq Hardware Development Link to the Zynq Minized Hardware development Blog Day 0 - MiniZed ZYNQ Day 0 - MiniZed ZYNQ FPGA Arrives Minized FPGA Board Concept and Basics Week 1: MiniZed ZYNQ Concept and basics Lab 0 Lab 1 and Lab 2 Setup Xilinx Vivado Week 2: Done!! Lab 0 Lab1 and Lab2 Lab 3 Lab 4 Lab 5 Peripheral Tests and Memory Tests Week 3: Done!! Lab3 Lab4 and Lab5 ...
nixiefairy

00-And so it begins..

Posted by nixiefairy Dec 29, 2018
Hey guys, So I received the MiniZed about four weeks back . It arrived during my final year exams which gave me no time to mess around with the board and the training material. Finally after my exams got over and a few celebrations (:P) I am ending off 2018 with this blog series. Before we dive into the material composition, I thought it might be best I introduced myself to the community : I am a fourth year undergrad currently studying Electronics and Computers Engineering. My experience with ...
I ran into a problem right away, my Xilinx software licenses were all expired for some reason, and the SDK would not start. Because of this, I downloaded Xilinx_Vivado_SDK_Web_2018.3_1207_2324_Win64 and installed a new image. I can now run the SDK again.  Maybe someone can instruct me how to "clean up" the license files. Vivado 2018.3 seems to start up faster BTW. The flow of the SW training modules is shown below.       The Objectives for SW Lab4 were similar to th ...
Note: This is part 6 of a series on working with FPGAs and in particular the Xilinx Zynq-7000S Programmable System-on-Chip with ARM Cortex-A9 processing core. For part 1, click here: Xilinx ZYNQ System-on-Chip - Getting to know the MiniZed Board For all parts, click here: Path to Programmable Note 2: Some of the diagrams in this series of blog posts by their nature need to be extremely dense, but are all reasonably high-res. Click to enlarge them, and then optionally save them (right-click) in ...
Welcome to the second half! This is the second half of the Zynq training series. The first half covered the "hardware" side of things; meaning the physical FPGA, the AXI Interface, and a fair amount of "TCL" (pronounced "tickle") interface. In the second half, we will start to write the "software" side which runs on the ARM Cortex processor portion of the Zync chip. In the diagram below, it will focus more in the grey area as the previous section focused a lot more in the yellow underlying "PL" ...
Note: This is part 5 of a series on working with FPGAs and in particular the Xilinx Zynq-7000S Programmable System-on-Chip with ARM Cortex-A9 processing core. For part 1, click here: Xilinx ZYNQ System-on-Chip - Getting to know the MiniZed Board For all parts, click here: Path to Programmable   Introduction What is Block RAM? How can Block RAM be used by the Processing System? Using the AXI Interconnect and Block RAM Creating Block RAM in Vivado Creating AXI Interc ...
We have received a materials for second module of Path to Programmable training. Here is agenda for the second module: In my opinion first three chapters from second module  covers the same material from first module. These three laboratories contain basic information about  Zynq architecture and Xilinx SDK. So, I will start second module from laboratory number four where we will learn more information about application development. ...
The structure for the second training module is as follows: Lab 00 was another installation guide, and I already had the required software installed. The Labs 01-03 were overviews of the SDK program and importing hardware information from Vivado. Since we already covered this in the ZynqHW training package, most of the information was redundant. New information included the HW file listing and more in-depth definitions of how the files are used. I purchased a TDNext 1.26Mpixel Pmod Cam ...
Hi Friends , In this Post we deal with Important Aspect in every design - "Debugging" . I would like to make this Post more generalized so that it can be applied to what ever Project you are working on it does not matter , for Reference i will use the PWM controlled LED design Project i posted here. You may not require to go there as i tried my level best to make this Self Contained with much smaller number of references as possible. Lets Dive Into Debugging . As always  in Our Top Down ...
Chapter 8 Video - SDK Project Management   This video was about project management in Xilinx SDK: workspaces & how to share/export them, how to import C/C++ files and set up repositories. Lab 8 - SDK Project Management  The export tool allows users to export their projects, breakpoints, launch configurations etc. to archive files. The exported files can then be imported to a new workspace/different computer. The import tool also allows C/C++ files to be imported. Chap ...
The next set of videos were centered around the Zynq-7000 boot process. In the previous labs, we programmed the PL & PS over JTAG, which requires an external master. Programming a bootloader to the non-volatile memory on the MiniZed allows it to boot-up and execute applications independently.   Chapter 6 Video - First Stage Bootloader  Zynq-7000 is a processor first solution: the PS boots first, and programs the PL.   When the PS boots up, CPU0 runs the initialization code ...
mconners

SW Module 4

Posted by mconners Top Member Dec 16, 2018
This lab was mostly more familiarization with the SDK.   The lab goals were stated as follows:   Add new software applications to SDK Use example code to target the UART in a Hello World application Apply example project templates, including       Memory Tests       Peripheral Tests Identify application code size and location Modify linker scripts to change the target memory location   So we started out by creating an empt ...
Continuing (off the course of the syllabus) from where Path to Programmable Blog 7 - Trying out a PL-only VGA design left off, I decided to try generating a HDMI/DVI video signal.   HDMI/DVI 101   VGA is an analog signal, where different voltages (from 0 to 0.7V) correspond to different intensities of color. Three wires (channels) are used to transmit R,G & B, and two 'sync' (HSYNC & VSYNC) are level triggered signals that control the scanning i.e. help the receiver determine ...
The videos & labs in Path to Programmable Blog 8 - Developing Zynq Software provided a brief intro to the software development workflow using Xilinx SDK. We now move on to the next set of videos which go over creating applications, using the Xilinx drivers and debugging.   Chapter 4 Video - Developing Applications The video picked up from where the chapter 3 video has stopped - the examples & documentation for the drivers that Xilinx provides for the Zynq peripherals. It then moved ...
In Path to Programmable Blog 6 - Hardware Debugging & some more TCL I finished Module 1 of Path the Programmable - Developing Zynq Hardware. Module 1 was centered around designing peripherals in the PL and interfacing them with the PS using Vivado, and now we move on to the software that will run on the PS.   Module 2 - Developing Zynq Software   Chapter 1 Video - Zynq System Architecture Basics  The introductory video went over the overall flow of software development for Z ...
Hi Friends , in the Previous post we have Created our own Custom PWM IP in Vivado and just Integrated it in our Design. In this Post we will run it On Minized Board. In the Next Post , I will show the Debugging Routes we will trace : For these functionalities we have added Integrated Logic Analyzer Core and JTAG to AXI master cores in our Block Design , I will Clear how these work in the Next post.   After Creating the Block Design with Our Custom IP added in Design this is no new Task ...
The first few labs in the SW Module are mostly a more in depth look at the SDK product provided with the Vivado Suite.   Lab 0 covers installing all the required tools. All of these steps were completed as part of the first set of labs, so there really wasn't anything to do.   They discuss the fact that the Editor is based on Eclipse IDE.   In Lab 1 they go into depth regarding the file we exported at the end of Lab 9 in the HW module. Z_system_wrapper.hdf. They explain that th ...
  I tried out a couple of things that weren't a part of the Path to Programmable Course Syllabus, but I thought I'd share them: How to setup the clocks for PL-only designs with the MiniZed 3-bit VGA output from the MiniZed without a PMOD.   MiniZed Clocking  As far as trial runs are concerned, running a PL-only design follows the same process as Xilinx's non-SoC parts like the Spartan & Artix: instantiate all HDL source code in a top level wrapper, assign the I/O pins (con ...
In the previous blog post Path to Programmable Blog 5 - Creating Custom IP , we created custom IP which comprised of some HDL code that implemented a PWM controller, which was then connected to the AXI bus as an AXI-4 Lite Slave, allowing the PS to control the PWM controller. We also added an Integrated Logic Analyzer and JTAG-AXI core.   HW Chapter 9 video: Vivado's Hardware Manager This video went over the different debugging techniques: Although the ILA is implemented in the FPGA fabr ...
In Path to Programmable Blog 4 - Adding a PL Peripheral & using PS DMA, we added Block RAM to the PL and connected it to the PS using the AXI interface. We also looked at how we can use DMA to speed up transfers. The Block RAM was added to the PL using Xilinx's IP that is bundled with Vivado - which was automatically configured and connected. When working on custom designs, we need to generate 'IP' of our own i.e. somehow link registers/datapaths in our HDL to the AXI interface so that th ...
About:Through Avnet, Xilinx and Element14, a training program to learn about the Zynq 7000 platform which is System On Chip combining an FPGA with an ARM processor. This comes to the students as complete development board packed with goodies like a wireless chip from MuRata (BT/BTLE/WIFI), 8GB Flash memory, onboard RAM, USB to JTAG (JTAG programmable over USB), Arduino-style headers (3.3V compatible only), Microphone, Bi-Color LED, and two additional expansion ports.   See all blog posts fo ...
You may remember when we left off, we removed the JTAG interface from our board design, but we left the PWM module and the Logic Analyzer, so the Block Design looked like this:     and I said something about next lab we would do some more TCL scripting and I guessed it would be about removing some IP that we added. BOY WAS I EVER WRONG.   They had us open Vivado, go to the TCL console, change directories into the support directory for lab 9 and type:   source ./lab9.tcl ...
In the preceding posts, we had a quick look at what Zynq-7000 is (Path to Programmable Blog 1 - Getting Started), the workflow (Path to Programmable Blog 2 - Xilinx Tool Flow & Getting Started with Zynq-7000) and we configured a couple of PS peripherals and ran tests (Path to Programmable Blog 3 - PS Peripheral Configuration & TCL). Now comes the important part: making the PL talk to the PS & DRAM, which will be used in probably every design that targets Zynq.   HW Chapter 6 vi ...
Path to Programmable Blog 2 - Xilinx Tool Flow & Getting Started with Zynq-7000 was an introduction to typical Zynq workflow: first configure the hardware (PS & PL) in Vivado, and then export it to Xilinx SDK to work on the software side of things. This blog post covers the next 2 sets of videos & labs: the first set covers PS peripheral configuration & the second one is a quick look at using TCL in Vivado. HW Chapter 4 video: Peripherals, Peripherals & more Peripherals! This ...