Path to Programmable Blog 2 - Xilinx Tool Flow & Getting Started with Zynq-7000 was an introduction to typical Zynq workflow: first configure the hardware (PS & PL) in Vivado, and then export it to Xilinx SDK to work on the software side of things. This blog post covers the next 2 sets of videos & labs: the first set covers PS peripheral configuration & the second one is a quick look at using TCL in Vivado.

HW Chapter 4 video: Peripherals, Peripherals & more Peripherals!

This video was mainly dedicated to explaining how the Zynq-7000's peripherals are organised, connected and how they need to be utilized.


The PS has a couple of interfaces implemented as hard IP (like a microcontroller). These interfaces aren't brought out directly because they are internally muxed, as shown in these diagrams taken from the Zynq-7000 TRM.

In short, some go thorough the 'MIO Multipexer' to connect directly to the PS I/O pins, while some have the ability to be routed to the PL (and PL I/O) via the 'EMIO' interface.


Here's where it gets a little more complex:

  • Some interfaces are solely available through the (direct) MIO interface i.e. they can't be routed to the PL I/O via the EMIO due to constraints like timing eg: USB.
  • Routing of pins needs to be done in groups eg: if SPI0 CLK is shifted, the remaining SPI0 pins also need to be shifted.
  • An interface cannot be split between MIO & EMIO, but unused pins can be left disconnected.




USB, QSPI and  the Flash cannot be routed to the EMIO, so naturally when assigning pins with the pinmux tool in Vivado, prioritize these interfaces by assigning them to the MIO first.

In most cases, when a peripheral is routed to the EMIO, everything will remain the same with a few exceptions eg. the MIO Ethernet  interface uses a 4-bit interface @ 250Mhz, but when routed to the EMIO it uses a 8-bit interface at 125Mhz.


The 7z007s (MiniZed) in the CLG225 packages supports only 32 MIO pins, but all other Zynq-7000 parts include 54 MIO pins. This restriction means that either USB MIO or Ethernet MIO is supported, SD card, NOR/SRAM are not supported and NAND Flash width is limited to 8 bits.


UG-585 (The Zynq-7000 Technical Reference Manual) has more details like how the signals are routed through the multiplexer (high speed signals go through only one stage), the logic levels and electrical parameters.



The next couple of slides were about the Zynq Address Map: where the SCU, DDR, MIO, General Purpose AXI ports, System Registers, Memory Controllers etc lie.

The address of most of these are fixed, with the exception of PL based peripherals which are automatically assigned by Vivado (although they can be modified)


Lab 3 - PS Configuration Part 2 - MIO Peripherals

This lab involved configuring the peripherals that were previously discussed.


{gallery} Peripheral Configuration

Quad SPI

USB Reset


Clock Configuration



After the MIO was configured, the clocks & PLLs were set. Since the block design was updated, the HDL wrapper needs to be regenerated. Just to make sure that nothing is left over from the previous wrapper, we 'Reset Output Products' - when similar to 'cleaning' a compiled project.

Next, the bitstream was generated as usual, but the minor recommended change was to explicitly set the location for the exported hardware & SDK workspace to prevent any issues from cropping up (instead of using the default location)

In Xilinx SDK, create a BSP as usual followed by a new application. This time in addition to the 'Hello World' template, also create and run 'Memory Tester' & 'Peripheral Test' templates.


HW Chapter 5 video: The Power of TCL

The Chapter 5 video was about TCL, which is a scripting language that is commonly used by EDA software. TCL is an interpreted language and can be used to automate tasks - performing any action in the Vivado GUI echoes the corresponding TCL command in the console.

As per the video, Vivado TCL combines SDC (Synopsys Design Constaints) and XDC (Xilinx Design Constraints) and is very well suited for scripting tasks, automatic timing analysis, generating reports etc.


Most importantly, everything created in a Block Design can be recreated using a TCL script - which makes it very useful for sharing configurations, making & restoring backups etc. since you don't need to use the GUI.

The last couple of slides were about the files that Vivado automatically generates: PS7_Init (C, TCL & HTML files which describe processor specifications - DDR config, clocks etc) & a .BD (block design).


Lab 4 - Using TCL in Vivado Embedded Designs


This was a short & simple lab since it was walk through of some of the different TCL commands that can be used on Vivado.


First, directory navigation: use the 'cd' command to navigate to the folder containing your project (remember to use forward slashes!)

'pwd' returns the present working directory & use can use 'dir' to list files.


cd C:/Speedway/ZynqHW/2017_4/ZynqDesign


Open your project

open_project ./ZynqDesign.xpr


Open the block diagram in the project

open_bd_design ./ZynqDesign.srcs/sources_1/bd/Z_system/


A couple of other commands for returning, creating & deleting external interfaces in the block diagram were covered.


This command exports the current design to a TCL file:

write_bd_tcl basic_design.tcl


This exports the TCL script that can re-create the current project

write_project_tcl -paths_relative_to C:/Speedway/ZynqHW/2017_4/ZynqDesign project_setup.tcl


This allows the entire project to be backed up & restored using the TCL files, which makes setting up a VCS easy.



HW Chapter 4 video: Peripherals, Peripherals & more Peripherals!

Lab 3 - PS Configuration Part 2 - MIO Peripherals

HW Chapter 5 video: The Power of TCL

Lab 4 - Using TCL in Vivado Embedded Designs


Next up:

HW Chapter 6 video: Merging the PS & PL

Lab 5 - Adding a PL Peripheral