About:

Through Avnet, Xilinx and Element14, a training program to learn about the Zynq 7000 platform which is System On Chip combining an FPGA with an ARM processor. This comes to the students as complete development board packed with goodies like a wireless chip from MuRata (BT/BTLE/WIFI), 8GB Flash memory, onboard RAM, USB to JTAG (JTAG programmable over USB), Arduino-style headers (3.3V compatible only), Microphone, Bi-Color LED, and two additional expansion ports.

 

See all blog posts for this training here.

 

Lab 9 - "The power of Scripting using TCL"

The final lab from Module #1 is talking more about TCL ("Tickle) scripting. There has been a fair amount of coverage of TCL in these labs - It was introduced right away in Lab 1, and Lab 4 was all about "The power of TCL" almost entirely dedicated to TCL. Lab 8 once again uses the TCL interface to "man in the middle" the FPGA (Program Logic / PL) commands directly rather than having to run software from the Processing System (PS) of the ARM processor. I think I get the point...

 

Question - are there any readers out there that use Vivado on a regular / professional basis? Are you using TCL the ways that the training shows? How else are you using it?

 

Here is a video that summarizes the lesson:

 

Here is the 'Before' image showing the output from the previous lesson; and startpoint of Lab 9:

This is what we see starting Lab 9 when we open the previous lesson.

 

 

We can see the Zynq processor, the AXI Interconnect; which only links to BRAM and the PWM Controller.

 

The TCL script is called via the "source" command; after changing the directory appropriately to find the file:

cd C:/Speedway/ZynqHW/2017_4/Support_documents/Lab9/
source ./lab9.tcl

After calling the 'source' command, it is "go make a sandwich" time - this took quite some time to finish. It looks like most of that was spent running the synthesized design and generating the bitstream; but there was definitely some downtime in there waiting for it to finish.

 

The Final result after running the TCL Script:

 

 

 

The program appears to only use a single core. The computer seems to move the thread around from core to core, but only one core is ever utilized at any given time. The training notes that running synthesis can take anywhere from 15-45 minutes. My computer was closer to the 15 minute mark but there were a few other steps like writing the bitstream that still had to happen.

 

 

Interestingly, running the Synthesize command takes a long time. An examination of Task Manager tells the story:

 

 

Once that is complete, this message appears; prompting to open the new design:

 

 

 

 

We now have PMOD connections (2x), a Wireless controller, a Bluetooth UART, and all the other requisite interconnects. Check out the video posted above for a walk through of all of this!

 

One potential downside of this method is that it was very 'directory dependent' - It took some messing around to get the directory structure correct for the script file to run correctly. Once that was done, however, it ran like a charm. Perhaps this could be compensated for in how the TCL scripting is created, but for this lesson it took a few extra steps to use the 'correct' directory instead of the directory I've been using up until this point.

 

Thanks again to E14 and Xilinx for this program! I'm very excited to start the next lessons in Module 2!

 

- James