Skip navigation
  I tried out a couple of things that weren't a part of the Path to Programmable Course Syllabus, but I thought I'd share them: How to setup the clocks for PL-only designs with the MiniZed 3-bit VGA output from the MiniZed without a PMOD.   MiniZed Clocking  As far as trial runs are concerned, running a PL-only design follows the same process as Xilinx's non-SoC parts like the Spartan & Artix: instantiate all HDL source code in a top level wrapper, assign the I/O pins (con ...
In the previous blog post Path to Programmable Blog 5 - Creating Custom IP , we created custom IP which comprised of some HDL code that implemented a PWM controller, which was then connected to the AXI bus as an AXI-4 Lite Slave, allowing the PS to control the PWM controller. We also added an Integrated Logic Analyzer and JTAG-AXI core.   HW Chapter 9 video: Vivado's Hardware Manager This video went over the different debugging techniques: Although the ILA is implemented in the FPGA fabr ...
In Path to Programmable Blog 4 - Adding a PL Peripheral & using PS DMA, we added Block RAM to the PL and connected it to the PS using the AXI interface. We also looked at how we can use DMA to speed up transfers. The Block RAM was added to the PL using Xilinx's IP that is bundled with Vivado - which was automatically configured and connected. When working on custom designs, we need to generate 'IP' of our own i.e. somehow link registers/datapaths in our HDL to the AXI interface so that th ...