Note: This is part 6 of a series on working with FPGAs and in particular the Xilinx Zynq-7000S Programmable System-on-Chip with ARM Cortex-A9 processing core. For part 1, click here: Xilinx ZYNQ System-on-Chip - Getting to know the MiniZed Board
For all parts, click here: Path to Programmable
Note 2: Some of the diagrams in this series of blog posts by their nature need to be extremely dense, but are all reasonably high-res. Click to enlarge them, and then optionally save them (right-click) in order to zoom even further into them.
If you’ve ever worked with a microcontroller and then wished it contained just one more timer or PWM module or some other hardware feature, then, like me, perhaps you’re interested in how to implement such devices for yourself using programmable logic! Any building-block you create could be called custom intellectual property (IP). This blog post covers how to get custom hardware (a PWM module in this case) onto a chip along with a microprocessor.
The is a compact board containing a Xilinx Zynq chip. The Zynq is a piece of silicon with on-board microprocessor (an ARM Cortex-A9) and programmable logic! The programmable logic can be used to implement arbitrary hardware, and the microprocessor can also interface to it if desired.
In the previous blog post, it was discovered how to get communication between the microprocessor (or Processing System or PS as Xilinx calls it) and the programmable logic (PL). It used an interface called AXI, that consists of read and write data busses and an address bus. All of this was mostly done using a graphical block view in the development environment called Xilinx Vivado. The graphical view shows each entity and the bundles of signals or internal routing that connects everything up. Xilinx supplies more than a hundred different ready-made graphical blocks, also known as intellectual property (IP) for use in designs. They are easy to use; just right-click in the diagram view and select Add IP, and then search the list. Once the block is placed, you can double-click it to open up a configuration options window. Any work required to complete the implementation, and signal connections to the rest of the design, can be automatically made by clicking on the green bars marked Run Block Automation or Run Connection Automation - they pop up whenever Vivado thinks you should run it!
Ordinarily when using the PL, a user would describe the desired hardware in a language such as Verilog or VHDL. In this blog post, a variant of AXI is used to connect to such arbitrary PL hardware. The source happens to be Verilog in this blog post, and it describes a pulse width modulation (PWM) circuit that dims an LED on the MiniZed board, based on a value that is selected by the microprocessor.
The purpose of this blog post is to examine how that programmable logic PWM hardware design can be turned into a graphical block that you can reuse in projects.
The PWM Module Hardware Design
A single file, called PWM_Controller_Int.v is supplied as part of the Zynq training course. I’ve reproduced it here since it is a very short piece of HDL content.
I’m not very familiar with Verilog, but basically this code defines a module which has several inputs and outputs. The output reg lines define registered outputs; in other words, there will be some flip-flops or memory that will latch values for those outputs.
Next, there are three blocks of content that all start with always @(posedge Clk). The thing in the brackets is the sensitivity list just containing one signal called Clk. The sensitivity list specifies that if that signal changes (in this case only positive edge changes) then the content in that block will be evaluated. All three blocks run simultaneously. The first block implements a counter with reset capability. The second block implements a binary comparator to test if the counter output is less than the value on the DutyCycle signals or not. The PWM output signal is the comparator output.
The third block implements another comparator that generates an Interrupt signal whenever the DutyCycle is set too high.
The aim of this blog post is to get this Verilog hardware description into a reusable graphical block. Along the way it will also be interesting to see what this description can look like once it has been converted or synthesized into logic.
Create New IP
In Vivado, click on Tools->Create and Package New IP, and follow the steps – they are straightforward, as shown below. An empty folder called ip_repo was specified for the custom IP (eventually this folder will contain a sub-folder for the custom IP). One of the steps allows you to select the PS-PL communication interface, and AXI-Lite was chosen.
After this has been completed, Vivado will have created a PWM_w_Int_1.0 folder (and several sub-folders inside that) in the ip_repo folder! It is now ready for editing, so that the VHDL or Verilog code can be added.
Go to Window->IP Catalog and you can search for the newly created IP, as shown in the screenshots below. Vivado will keep any existing project open, and will open up a whole new Vivado instance for editing the Custom IP. In other words, custom IP is treated like a whole new project.
Once the steps above are complete, a couple of VHDL files will be present in the project source window. The top-level VHDL file for the project will reference the second file, which contains the AXI-Lite slave. The top-level file in this example was automatically called PWM_w_Int_v1_0.vhd
Adding your HDL Content
The PWM module HDL file is placed in the hdl folder that is inside the sub-folder that was created by Vivado, as shown in the steps diagram below. Next, Add Sources is selected within the Flow Navigator pane on the left side of Vivado, and click-through as shown below to get the file added!
When your HDL content (for example in Verilog or VHDL) is added to this Custom IP project in this manner, the top-level VHDL file that was automatically created earlier will need some editing to declare the (a) the signals or ports, (b) declare the PWM module component, and (c) instantiate the component. Just as a refresher (it was discussed in blog 2) the diagram below shows the areas within VHDL where (a)-(c) would need to be entered.
The code below shows the final top-level file PWM_w_Int_v1_0.vhd content. The stuff that was manually added to incorporate the custom PWM module Verilog code is highlighted. You can see it isn’t much.
A couple of additions are needed in the AXI-lite VHDL file too. The entire file is shown below, and the two changes are highlighted.
Once all these changes have been made and saved in Vivado, the Source window will show the AXI-lite and the PWM module Verilog file both indented, underneath the top-level VHDL file.
Synthesize the Custom IP
The hardware description in the source files needs to be converted into a lower-level design. Click on Run Synthesis and click through as shown in the screenshots below to achieve this.
Although it’s not essential, (and it would be harder to interpret for a more complicated design) it is possible to explore the schematic to see what the synthesis engine in Vivado did.
The screenshot below shows the majority of the top-level schematic (it is large so a bit of it had to be snipped off the screenshot for clarity). The two blue blocks represent the Verilog PWM module, and the AXI-Lite hardware.
Double-clicking into the PWM blue box, it is possible to explore and see how the Verilog code got translated into lower-level logic.
Packaging the Custom IP Project
Some housekeeping stuff is required, to get the block ready to be usable in any Vivado project. The types of things that need to be done include indicating to Vivado which configuration parameters should be present when the user double-clicks on the block to edit the IP for instance.
All the things that need to be done are listed in a Packaging Steps list that appears when Package IP is clicked in the Flow Navigator on the left side of Vivado. The user needs to click through each of the steps, completing anything as required.
The packaging step titled File Groups needs most work however, and it is caused by the fact that this VHDL example Custom IP project includes Verilog source in the mix, and Vivado doesn’t automatically handle it as it should. There are folder paths with names like VHDL Synthesis, VHDL Simulation, Verilog Synthesis and Verilog Simulation that would ordinarily be used if there wasn’t a mix. However, if there is a mix, then the folders that should be used are to be called just Synthesis and Simulation, and it becomes the user’s task to create these, and add the files there (and delete the incorrect folders). Surprisingly Vivado makes this quite awkward, when at worst case it ought to be a drag-and-drop or simple folder renaming exercise. The messing around is impressive, and it is a lot of steps. Anyway, the steps are shown in the screenshots below.
The PWM period setting is a hidden parameter, and it can be set to become visible in the GUI as shown in the steps below. Vivado also has the capability to recognise or infer certain signals (such as clock and reset) from the custom IP. This is helpful when making and checking connections. For this reason, in the case of the custom IP used in the example here, the Interrupt_Out signal is marked as being of type Interrupt as shown in the steps below too. Finally, in the Review and Package step, the Package IP or Re-Package IP button is clicked to complete it all!
After all this, the sub-folder in the original folder (called ip_repo) that was created at the start of this blog post, will contain everything for the custom IP!
In the next blog post, this custom IP will be used!
It was great to see that graphical building blocks for custom IP are reasonably straightforward to create. Vivado creates a whole new project window for it, where the user can add their source HDL file, synthesize it, and then follow some packaging steps to make the GUI for it to be usable.
As part of the exercise, it was interesting to see how the source HDL code (in this case Verilog) was used in the top-level VHDL file, and how Vivado can display a schematic view after synthesis, which can be explored.
Thanks for reading!