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Overall Impressions   Well, I'll have to say this was a very interesting process. There were some delays, which collided with my schedule, there were some bumps, and there were some unexpected surprises. All of which come together to explain how we learn things.   First off let me say thank you to Element 14 and Randall for putting this opportunity together. Thanks to Avnet for making the training materials available to us. For those of you who hadn't figured it out, or who were inte ...
I made this post because i found the example code provided in SDK for I2C is not meant for Minized , if it is not realized then it would be frustrating in figuring it out. I am not going to show how to modify that given(Buggy) piece of code but i change it to make it work (yeah its Working) , i found different alternatives and  I would like to show the Best one which is Easy to Understand and Implement/Change for our Purpose. Before Going into It,we need to understand few things such as H ...
Hey folks, ZynqHW_2017_4_lab_6_v12.pdf  So let's continue our arduous journey through the lab manuals. Boy, aren't things spicing up a bit? So the first part of lab 6 shows us to import our SDK files done from Lab 3. The main aim was just to show us how to import lab files. So in all fairness, we won't be needing those lab files. The next part talks about importing a pre-made C file which executes the following steps : Number of words the user wants to transfer The manner in which thes ...
Download Resource Files from  Github: https://github.com/uElectron/minizedSDK ====================================================================== In this Video , using the Minized Board based on Xilinx Zynq : 1.)We review about the First Stage Bootloader  and its requirement. 2.)We then Generate a Boot Image for QSPI using Bootloader,Bit Stream and Led Blinking Application using Boot Gen provided in SDK. 3.)We then Flash the Boot Image Onto the Minized QSPI Board . 4.)We th ...
Download Resource Files from Github: https://github.com/uElectron/minizedSDK ====================================================================== In this Video , using the Minized Board based on Xilinx Zynq : 1.)We test the Application which Blinks PS LED controlled with PS Button by using Interrupts instead of Polling and We can Observe a Changing Pattern in LED Blinking 2.)We run PL LED Blinking Application by using the GPIO driver in PL based on the Hardware Design by modifying a singl ...
In this Video , using the Minized Board based on Xilinx Zynq : 1.)We Develop Application which Blinks PS LED controlled with PS Button by using Interrupts instead of Polling and We create a Changing Pattern in LED Blinking 2.)We Develop PL LED Blinking Application by using the GPIO driver in PL based on the Hardware Design 3.)We can see how to use Example Programs to develop our own Interrupt Based Applications. 4.)We see the possible Pitfalls and Bugs we may encounter when using example Pr ...
The Module 2 of the MiniZed Path to Programmable is focused on software development in xilinx fpga. The previous minized SW development ZYNQ blog can be read here The Hardware related blogs are here Summary of Module 1 Path to Programmable ZYNQ HW blogs The Software related blogs are here Summary of Module 2 Path to Programmable ZYNQ SW blogs   ZYNQ SW Module Lab 10  In this lab, an application which reads and writes MAC address (EUI-48 only) configuration data to/from the on-board Q ...
The Module 2 of the MiniZed Path to Programmable is focused on software development in xilinx fpga. The previous minized SW development ZYNQ blog can be read here The Hardware related blogs are here Summary of Module 1 Path to Programmable ZYNQ HW blogs The Software related blogs are here Summary of Module 2 Path to Programmable ZYNQ SW blogs   ZYNQ SW Module Lab 8  Aim: Develop ZYNQ software with SDK Project Management. This shows the basics such as how to share or archive a collec ...
The Module 2 of the MiniZed Path to Programmable is focused on software development in xilinx fpga. The previous minized SW development ZYNQ blog can be read here ZYNQ-SW Module 2 Minized Blog3 --lab4 & lab5 The Hardware related blogs are here Summary of Module 1 Path to Programmable ZYNQ HW blogs The Software related blogs are here Summary of Module 2 Path to Programmable ZYNQ SW blogs   ZYNQ SW Module Lab 6 ZYNQ SW Module Lab 7 Conclusion   ZYNQ SW Module Lab 6 ...
Hey everyone.,   ZynqHW_2017_4_lab_4_v11  So let's continue onward with setting up our basics for TCL. After a brief read through the lab, I plan to use Vivado in tcl mode (non GUI mode). Let's see if we can change ports in a block diagram without seeing a block diagram [hehehe]. Below is a gallery of the output I got from the tcl console. Feel free to have a look at the solution code given at :my repo: Lab 4 slideshow Where is the BD file located : block diagram Opening pro ...
kk99

[PP-21] ECG signal filtering

Posted by kk99 Jan 15, 2019
I have created with usage of FIR compiler IP a simple low pass filter. The low-pass filter is described by the formula: y(n) = 2y(n-1)-y(n-2)+x(n)-2x(n-6)+x(n-12). It has cut frequency around 11 Hz. I have used it for filtering and denoising a ECG signal. Here are example signal before and after filtering: ...
  In this video we can see how we can implement any Peripheral functionality into Our Application, it is explained it by means of UART peripheral as an example. We can see how the code is Implemented, how to select it and use them from the available example code. We can also see the Potential Bugs we may trap into when working on Program code using templates. We can see how the Practical Designers Develop Applications and how the code Development time can be Reduced to a large extent wh ...
rsc

MiniZed with TD114 Case

Posted by rsc Jan 14, 2019
I made up a new case for the MiniZed with the video card installed. I need to revise the cover with cutouts for the USB connector and the two jumpers on the video board. Each half was a 5 hour print. Scott ...
In this Video,I have shown the Step by step Procedure of working on Xilinx SDK for Developing Software Application for Minized and also given the Details pertaining to functionality of various blocks and  Necessity of various files.   It Answers to Aspects relating to: What do Hardware Definition File contains? Necessity to Import .hdf file? How SDK provides the Hardware Design Details to the Software Developer ? How Software Programmer can used Memory Mapped Register ? Why and H ...
Hey everyone,   ZynqHW_2017_lab_3_v13.pdf   In lab 3 we will start discussing the other Zynq blocks in detail. The lab starts with introducing the selection of boot device. The QSPI memory interface (Quad Serial Peripheral Interface) is a SPI (another asynchronous serial communication protocol) module which has a memory mapped register interface, which allows direct interface for accessing data from external SPI devices and thus simplifying software requirements. The bootup of the QS ...
To control my camera module, I'm going to use a X-Y gimbal made from RC servos. I will run the servos from the MiniZed. To do this, I have modified the code from the IP training to run two RC servos instead (and addition to) the PL leds. The new Vivado Block Design is as follows: I added another instance of the IP PWM_w_Int, and connected it to PL_LED_G The new address of the second PWM channel (Green LED) is 0x40002000: The green and red PL LED pins are also available on the Arduino ...
The main purpose of lab 10 and 11 is to get familiar with Xilinx libraries and Pmod (Peripheral Modules )   1. Create the application project In this part we will learn how works example application which reads and writes MAC address configuration data to/from on-board QSPI flash device. We need to create a new empty application project similar to previous laboratories. Then we need to import a source file provided with support documents. We need to modify a BSP to enable support for Xil ...
kk99

[PP-19] Lab 9 - Interrupts

Posted by kk99 Jan 12, 2019
The main purpose of this lab is to get familiar with Interrupt Service Routine. We will see how interrupts works based on example with PWM LED dimmer.   1. Create the Interrupt application project We need to create a new empty application project similar to previous laboratories. Then we need to import a source file provided with support documents. It is simple application which allow to change the brightness of LED D8 from terminal input. It handles the invalid value of brightness in ...
The main purpose of this lab is to get familiar with built-in functionality for creating a SDK project archive.   1. Create a complete SDK Project archive In SDK please choose option File -> Export. Select General -> Archive File and select Next. On next screen choose button Select All and enter name of archive. Then press Finish. In the same way we could export information about Launch Configurations or Breakpoints. 2. Importing of shared project archive To import projec ...
In this lab we will learn how create a boot image for QSPI and boot from it with usage of FSBL. We will create boot image for test peripherals application and boot it from non-volatile memory.   1. Create the QSPI boot image To create a boot image please select: Xilinx Tools -> Create Boot Image. BIF (Boot Image Format) is the input file into Bootgen that list the partitions which Bootgen is to include the image. The BIF also includes attributes for the partitions. The output format ...
First Stage Boot Loader application configures the FPGA with HW bit stream and loads operating system image or standalone image or second stage boot loader image from non-volatile memory (NAND/NOR/QSPI) to RAM and starts executing it. In this lab we will learn how to generate a FSBL application using template.   1. Generate the FSBL In SDK please choose Files -> New -> Application Project. Provide name and choose option to create a new BSP. From templates please select a Zynq FSB ...
The purpose of this lab is to upload a example application from the SDK to the hardware through a JTAG connection (This part is similar to the laboratory number two from first module). Additionally we will get familiar with software debugging.   1. Configure the SoC PL with bitstream At the beginning we need to configure a hardware and set proper boot mode. We need to enable JTAG boot. We need to enable JTAG boot. It could be done by setting dip switch to position J. Here is picture of th ...
Before Starting to work on Minized with Xilinx SDK , we need to get Acquainted with at least some Hardware Aspects of Minized ,in order to prevent possible Confusion. If you guys have Already followed my Hardware Design Posts , you can skip to  "Now What are we Going To Do with Software Development" section at the Bottom For those who are new to Minized I recommend you guys to first Go through this Post for getting a big Picture perspective :   First of All What is Minized Board ? ...
In this lab we will learn how to add a new software application to SDK based on examples with Hello World and Memory/Peripheral tests applications.   1. Start of development based on example code Please launch Xilinx SDK and choose: File -> New -> Application Project. Please enter the project name and use exiting Standalone BSP. When you press Next you will see a list of available templates. In this lab we will use a Empty Application template. By choosing other template like: Me ...
Well - I finally managed to do it! I have created a basic project based on the lessons from the training.   About:Through Avnet, Xilinx and Element14, a training program to learn about the Zynq 7000 platform which is System On Chip combining an FPGA with an ARM processor. This comes to the students as complete development board packed with goodies like a wireless chip from MuRata (BT/BTLE/WIFI), 8GB Flash memory, onboard RAM, USB to JTAG (JTAG programmable over USB), Arduino-style header ...
This is an update on where my project is at.   My initial intent was to rebuild a line follower that I did back like 8 years ago; but using the MiniZed. The board is very well suited for this application - the PL (FPGA) can do all the grunt work of reading dual wheel encoders, running a control loop to feed a PWM signal back to the motors. Since the board offers a whole host of other goodies like the MuRata bluetooth & Wifi module, then a web interface could be added. We could use the ...
Hey guys, Hope this new year brings luck and fortune to everyone!   ZynqHW_2017_4_lab_1_v11 :   So I would just cover briefly Lab 1 : Guides to setup a new project. I didn't like the fact Avnet is forcing it's users to select target language as VHDL. Would have been great if they could leave the decision up to the reader. So ignoring this particular instruction , I went ahead with Verilog.       2. After selecting the correct target device, a new Zynq project ...
This blog will cover the final two lessons in the Speedway Series for Software on the MiniZed. We'll talk about the built-in libraries and go through using the PMOD headers.   About:Through Avnet, Xilinx and Element14, a training program to learn about the Zynq 7000 platform which is System On Chip combining an FPGA with an ARM processor. This comes to the students as complete development board packed with goodies like a wireless chip from MuRata (BT/BTLE/WIFI), 8GB Flash memory, onboard RA ...
In this post we get through labs 8 and 9. This will teach us how to archive a project and restore from archives; then it will discuss using interrupts in our programs.   About:Through Avnet, Xilinx and Element14, a training program to learn about the Zynq 7000 platform which is System On Chip combining an FPGA with an ARM processor. This comes to the students as complete development board packed with goodies like a wireless chip from MuRata (BT/BTLE/WIFI), 8GB Flash memory, onboard RAM, USB ...
My project is to do something interesting with the PMOD TDM114 camera module. I found a demo project on the Avnet site called "MJPEG Video Streaming on Avnet MiniZed" It looks like exactly what I needed to start this project, so I downloaded the quick start guide. The first thing to do was Flash the boot image boot_QSPI.bin to QSPI.  There is a command line tool for this in the SDK package. I used the hardware platform and First Stage Boot Loader (fsbl) from the ZynqSW labs and it f ...
The list of the step by step zynq software development blog learnings and projects are as below     Topics in the minized ZYNQ software development Link to the minized software development blogs Introduction to zynq SW development and Vivado SDK Application development ZYNQ-SW Module 2 Minized Blog1  -- Labs 0 1 2 Developing Zynq software with Xilinx SDK using standalone Board Support Packages BSPs. ZYNQ-SW Module 2 Minized Blog2 -- Lab 3 SW applications for the Hardware platform ...
The Module 2 of the MiniZed Path to Programmable is focused on software development in xilinx fpga. The previous minized SW development ZYNQ blog can be read here ZYNQ-SW Module 2 Minized Blog2 -- Lab 3 The Hardware related blogs are here Summary of Module 1 Path to Programmable ZYNQ HW blogs The Software related blogs are here Summary of Module 2 Path to Programmable ZYNQ SW blogs   ZYNQ SW Module Lab 4 SW Module Lab 4 Experiment 1 SW Module Lab 4 Experiment 2: Peripheral Te ...
The Module 2 of the MiniZed Path to Programmable is focused on software development in xilinx fpga. The previous minized SW development ZYNQ blog can be read here ZYNQ-SW Module 2 Minized Blog1  -- Labs 0 1 2 The Hardware related blogs are here Summary of Module 1 Path to Programmable ZYNQ HW blogs The Software related blogs are here Summary of Module 2 Path to Programmable ZYNQ SW blogs   ZYNQ SW Module Lab 3  This lab is about developing Zynq software with Xilinx SDK using ...
Hello again! In this post, we'll /finally/ upload to the physical MiniZed AND get it to boot up on its own running a program.   About:Through Avnet, Xilinx and Element14, a training program to learn about the Zynq 7000 platform which is System On Chip combining an FPGA with an ARM processor. This comes to the students as complete development board packed with goodies like a wireless chip from MuRata (BT/BTLE/WIFI), 8GB Flash memory, onboard RAM, USB to JTAG (JTAG programmable over USB), Ard ...
Hello again, In lab 5 we finally connect the MiniZed and flash it with a program! Closely followed by lab 6 in which we set up the first stage bootloader - FSBL. This will allow the MiniZed to run "untethered" and not plugged in with the JTAG connector to the computer run our program.   About:Through Avnet, Xilinx and Element14, a training program to learn about the Zynq 7000 platform which is System On Chip combining an FPGA with an ARM processor. This comes to the students as complete de ...
Finished the second module training course today with minimal headaches. Lab 8 objectives: This lab came in handy, because I messed up something during lab 10 and I had to revert to the archived workspace from lab 8. Whatever I did, the SDK will no longer load with SDK_Workspace selected.  I'm going to compare files later to see if I can find the problem. Lab 9 objectives: This lab was a modification of the LED_PWM project from ZynqHW project to add some exception checking and reco ...
For my Path to Programmable project, I wanted to build something that would use both the PS & PL of the Zynq-7000. The original plan was to build a logic analyzer that used BRAM & DRAM as a sample buffer, but I realized that I might not get it to work before the deadline.   In search of something simple, I decided to build a WS2812 controller. The WS2812 RGB LED uses a single wire serial protocol that infers '1's and '0's by varying the width of a pulse. WS2812s can be driven fro ...