The Module 2 of the MiniZed Path to Programmable is focused on software development in xilinx fpga. The previous minized SW development ZYNQ blog can be read here ZYNQ-SW Module 2 Minized Blog2 -- Lab 3
The Hardware related blogs are here Summary of Module 1 Path to Programmable ZYNQ HW blogs
- ZYNQ SW Module Lab 4
- SW Module Lab 4 Experiment 1
- SW Module Lab 4 Experiment 2: Peripheral Test
- SW Module Lab 4 Experiment 3: Add and Edit Memory Test
- ZYNQ SW Module Lab 5
- Lab 5 Exp1: Setup Hardware and Download Bitstream
- Lab 5 Exp2: Running an Application
- Lab 5 Exp3: Running Memory Test Application
- Testing the application Test_Memory_FullDDR
- Results from the Peripheral Test application
ZYNQ SW Module Lab 4
In this lab I added the application as the Hardware platform and BSP, we are now ready to use. The BSP generated and drivers for all peripherals in our workspace.
Lab 4 Objectives
When you have completed Lab 4, you will know how to:
• Add new software applications to SDK
• Use example code to target the UART in a Hello World application
• Apply example project templates, including
- Memory Tests
- Peripheral Tests
• Identify application code size and location
• Modify linker scripts to change the target memory location
SW Module Lab 4 Experiment 1
Here I add an empty software application by using the existing Hello World example code with the UART driver. Then generate the linker script which targets the application memory region.
Creating a new Hello zynq project with Hello world template
Many examples that can be used from xilinx
Looking into the size of the generated elf file. Size of the Hello_Zynq Application
The lscript.ld file is the linker script for the application. Here below one can see the report where the memory which were used in the application. This linker file is changed to change the location of the application as seen later.
The lscript.ld file with a summary of the available memory locations
The lscript.ld file further described
source linker script code from which the Summary was generated
Generate Linker Script can be used to edit the memory location as shown above
ps7_ram_0 is selected to place the code Heap and Stack into. The Linker Script Generator defaults to 1 KB for Heap Size and Stack Size
Result after building the Linker Script again. SDK rebuilds the Hello_Zynq application based on the new linker script. All the changes can be seen in the newly generated lscript.ld file
SW Module Lab 4 Experiment 2: Peripheral Test
Here we added the Peripheral Test application in the existing SDK workspace. This is also done using the existing standalone_bsp_0 and the Template Peripheral Tests.
using the Peripheral Test application from xilinx
The peripheraltest.c file
Looking at the CacheEnable() functions to enable both the L1 and L2 caches.
SW Module Lab 4 Experiment 3: Add and Edit Memory Test
There is also an application template for Memory Test in SDK. This is a test for any new hardware system to make sure the memory is stable prior to running an O/S. Testing the Test_Memory_FullDDR here as shown below. Similar steps from above are followed. Later the code is edited to test FullDDR memory.
The lab 4 has ended here. A summary of all the zynq software SDK labs can be found here Summary of Module 2 Path to Programmable ZYNQ SW blogs
ZYNQ SW Module Lab 5
The aim here is to connect SDK applications to Hardware on Minized. We connect to hardware through a JTAG connection. The bitstream is programmed into the PL & after the ARM processor configuration the code boots to the memory. SDK runs the application on top of the hardware and can be also used for debugging.
Lab 5 Exp1: Setup Hardware and Download Bitstream
Set Boot Mode jumpers to Cascaded JTAG Mode
The SDK already choses the correct bitstream depending on the chosen project in the SDK. Click Program
Lab 5 Exp2: Running an Application
Run the Hello_Zynq and Test_Memory applications on the hardware, viewing the results.
Testing the Hello_Zynq Application on the Minized
Viewing the results of the Hello_Zynq
Running the applications on minized
Lab 5 Exp3: Running Memory Test Application
View the memory test results on the minized as above
Testing the application Test_Memory_FullDDR
Steps to set up the environment and the results are shown below.
As shown the above steps can be repeated and all the software applications are tested on the minized board.
Results from the Peripheral Test application
In labs 4 and 5 different application projects were created in Vivado SDK using the standalone_bsp_0. And later these tests were run on the minized hardware using the memory test template code. A Summary of all the ZYNQ minized SW bloags can be read here Summary of Module 2 Path to Programmable ZYNQ SW blogs