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The main purpose of lab 10 and 11 is to get familiar with Xilinx libraries and Pmod (Peripheral Modules )   1. Create the application project In this part we will learn how works example application which reads and writes MAC address configuration data to/from on-board QSPI flash device. We need to create a new empty application project similar to previous laboratories. Then we need to import a source file provided with support documents. We need to modify a BSP to enable support for Xil ...
kk99

[PP-19] Lab 9 - Interrupts

Posted by kk99 Jan 12, 2019
The main purpose of this lab is to get familiar with Interrupt Service Routine. We will see how interrupts works based on example with PWM LED dimmer.   1. Create the Interrupt application project We need to create a new empty application project similar to previous laboratories. Then we need to import a source file provided with support documents. It is simple application which allow to change the brightness of LED D8 from terminal input. It handles the invalid value of brightness in ...
The main purpose of this lab is to get familiar with built-in functionality for creating a SDK project archive.   1. Create a complete SDK Project archive In SDK please choose option File -> Export. Select General -> Archive File and select Next. On next screen choose button Select All and enter name of archive. Then press Finish. In the same way we could export information about Launch Configurations or Breakpoints. 2. Importing of shared project archive To import projec ...
In this lab we will learn how create a boot image for QSPI and boot from it with usage of FSBL. We will create boot image for test peripherals application and boot it from non-volatile memory.   1. Create the QSPI boot image To create a boot image please select: Xilinx Tools -> Create Boot Image. BIF (Boot Image Format) is the input file into Bootgen that list the partitions which Bootgen is to include the image. The BIF also includes attributes for the partitions. The output format ...
First Stage Boot Loader application configures the FPGA with HW bit stream and loads operating system image or standalone image or second stage boot loader image from non-volatile memory (NAND/NOR/QSPI) to RAM and starts executing it. In this lab we will learn how to generate a FSBL application using template.   1. Generate the FSBL In SDK please choose Files -> New -> Application Project. Provide name and choose option to create a new BSP. From templates please select a Zynq FSB ...
The purpose of this lab is to upload a example application from the SDK to the hardware through a JTAG connection (This part is similar to the laboratory number two from first module). Additionally we will get familiar with software debugging.   1. Configure the SoC PL with bitstream At the beginning we need to configure a hardware and set proper boot mode. We need to enable JTAG boot. We need to enable JTAG boot. It could be done by setting dip switch to position J. Here is picture of th ...
Before Starting to work on Minized with Xilinx SDK , we need to get Acquainted with at least some Hardware Aspects of Minized ,in order to prevent possible Confusion. If you guys have Already followed my Hardware Design Posts , you can skip to  "Now What are we Going To Do with Software Development" section at the Bottom For those who are new to Minized I recommend you guys to first Go through this Post for getting a big Picture perspective :   First of All What is Minized Board ? ...