Overall Impressions


Well, I'll have to say this was a very interesting process. There were some delays, which collided with my schedule, there were some bumps, and there were some unexpected surprises. All of which come together to explain how we learn things.


First off let me say thank you to Element 14 and Randall for putting this opportunity together. Thanks to Avnet for making the training materials available to us. For those of you who hadn't figured it out, or who were interested, it seems that the training material were available from the minized.org site, if you did a bit of digging. They were listed under Speedway training and from what I saw they were the same materials. I did not include a link because you have to register to get access to them, and it's probably more fun to go digging around the site and see what else they have.


Now lets discuss the training a bit. The idea was to take a bunch of people of varying backgrounds, especially those without a bunch of FPGA background and see how much they could learn about programming FPGAs. My background was I was exposed to programmable logic back in the early 90's, it was kind of in it's infancy, but I got an idea of what it was about and got some exposure. I haven't touched programmable devices to any significant degree since that time. I can say the basic concepts are the same, but the capacities of the devices has grown a lot. The things that you can do inside these chips now is amazing.


While I learned a lot in the training, I do not at this point feel qualified enough to put FPGA experience on my resume. I think it would take quite a bit more exposure than I gave and that was expected for the training. It did give me the capability to take a much more advanced example and to be able to implement it. My plan for  my project was to utilize the built in microphone to maybe build a rudimentary guitar tuner. Take the microphone input, do an FFT on the data, and display that somehow. I really wasn't even concerned about displaying the frequency at first, just a spectral display of the time domain data would have been adequate. One big hurdle was that the minized board has no display, so that really put a crimp in my plans. So I was going to settle for at first, at least for this project, just to capture the data, and display it elsewhere. It would have given me the experience with the design elements I was looking for. And that's what really what training and experimentation is all about.


Ok, now lets talk about my project and what I really did end up with.


The Microphone Sub System


The microphones included on the minized board are surface mount ST MP45DT02MP45DT02 MEMS (Micro-Electro-Mechanical Systems) connected directly to Zync - 7000 AP SoC on the MiniZed board. It can take the PDM (pulse density modulation) from the microphone and convert it to 16 bit PCM (pulse code modulation) in two's complement format at a decimated sampling rate suitable for audio. Ok, I quit. That sounds too hard already. Just kidding, I found an example project that would help me.


I happen to have a version of MATLAB, which was necessary to conduct this experiment. That, along with System Generator utility of the Vivado design suite allow you to model circuits in MATLAB, using Xilinx IP blocks, and then export that design out to Vivado to program the FPGA.



You can see this is an Avnet design. I just borrowed it. Diving deeper into the Green Box we find



the Low Pass 64x Decimation Filter, the output of which goes to a scope, and to a High Pass Filter, the output of that goes to CEProbe, which can be used in the Vivado Software to trigger data capture. Remember that, it's important later.


Now that we have created the design using MATLAB, we can click on the System Generator block (the Red Xilinx logo above)



Notice the board is not selected, but the Chipset we have is in the Part: box is. That is the part number for the Zync Chip on the minized. Now this is where my plan started to fall apart. I didn't realize it at the time, but when I selected generate above, it seemed to run without errors. I checked the target directory specified, and there were output files, so I thought I was good to go. So I proceeded, I wanted to get through this lab as is, then come back and modify it to add the FFT IP. Somewhere between this step and coming back to add the FFT IP, I had to upgrade my version of linux, and subsequently my version of MATLAB. When I tried to regenerate the IP using sysgen, I was given an error that I did not have the appropriate license for XIling to use the System Generator, and my research showed the cost was ~$1000. So, subsequently, my project ended up being this experiment, but I don't mind, I tried, and I failed. That's part of being a scientist. At any rate I will continue to document the rest of this experiment.



Applying what I learned in the course materials:


The next part of this would have had me completely lost had it not been for going through the exercises provided in the course work. They had us navigate to  a scripts directory that had been downloaded with the rest of the project and DO WHAT!? Execute the TCL Shell. TCL me with a feather:



My directory was a little different cause I'm on a linux system




Now this was where I was glad I went through the course. The very first thing I got was a TCL error that I was using the wrong version of Vivado. So I updated the version number and tried again. I was not afraid to get in there and start making changes. Then it complained about the Board Definition File not being included, so I had to find that, which I found by googling around. There were other errors here and there, but I got through them all, which would not have possible without the training.

The process took about 20 Minutes to complete once I had clear up all the errors.


then we entered the TCL command:




which guess what, it started the GUI.


I was directed to open the Block Diagram, which we always did in the training, but WOW, they had populated almost everything you could. I'm still not sure if it was the Board Definition File I found, or if it was just the scripts said, "Hey let's configure every part we can find on this thing", something to research. I think it's a combination of both. Anyways here is the stuff that is important:


The 4 pertinent blocks are microphone_mgr_0,

pdm_filter_sysgen_0, that's the stuff we made (or I thought I made) in MATLAB,

ila_0, logic analyzer, we played with that in the labs

ila_1, another logic analyzer


Hey, notice that orange line, I highlighted it for you, that's the CEProbe line I said we could use to trigger data capture. I told you not to forget.


OK, you also might be saying, "Hey, why didn't you add the FFT IP in here?", I tried. I added the FFT Block, wired it up, said I didn't have a license for the IP. Grrr. So I went for the free DFT hooked it up, everything was going great, but then I ran out of gates. I tried deleting a bunch of stuff off of the diagram, but I had no success, I had to cut my losses and get around to writing up my project.


So, anyway, they had us go through and run some reports, I wont bore you with the details, it was stuff we had seen during the training. More repetition is good, right.


Finally, they had us export the Hardware and the bitstream, we know what that means, right? It means heading over to the SDK. Did that a million times in the training. Interestingly enough, all we did was create a board support package, create an empty HelloWorld project, program the FPGA, then exit the SDK and go back to the Vivado program and execute the Hardware Manager, so we could get to the Integrated Logic Analyzers. We did that in the training  I believe.




Ok, so they had me set the trigger minized_foundation_i/pdm_filter_sysgen_0_audio_ce == 1



Directed me to place a sound source near the board, I used a tone generator i downloaded for my phone, set the tone to 1khz, started the capture,



As you can see it captured somewhat of a tone. I didn't check it with an oscope or anything, but it seems reasonable to be about 1Khz.


They then give me the option of exporting the data to a CSV file




Now that I've got a csv file, I can open MATLAB again and analyze the signal



You can see the tone is centered around the 1Khz mark, and the estimated frequency is 1001.358 hz


Just for fun, I'll repeat the capture with a 440hz signal



And again with the MATLAB



So I'd say that's a pretty reasonable capture and estimate.





So I learned a lot out of taking this course. I didn't learn everything I thought I would. I lacked the ability to complete the final project that I planned. Some of this was due to licensing, some of it was due to lack of experience.


Is it something that I think I could complete with more exposure and education? Yes, it may have just been a bit ambitious for this project.


Do I know more about FPGAs and the Zync-7000 series? Absolutely.


Do I feel that I could create a design from scratch and implement it without examples to drive me? No, I did not gain that much experience.


Is there more I can learn about this chip and it's capabilities? No doubt, this is a powerful architecture an we just scratched the surface.


Do I feel bad that I was unable to achieve my design goals? No, not really, I think I just over anticipated what would be possible.


Would you do it again? I certainly would. This was one of the funner more challenging things I have attempted in quite a while.


As I mentioned, this really challenged me. Not mentally, it wasn't difficult, just in terms of how much time you would need to invest to really understand this completely.

The things I was exposed to for the first time include:


Detailed FPGA design

integrated FPGA and microprocessor

Certain MATLAB functions and scripting



Vivado SDK

Things I have probably forgotten


The things I was reintroduced to after a many year absence


FIR Filters



I really do think it was a great experience. I do know a lot more about the subject matter than before I started. As I mentioned, I don't think I can put FPGA designer on my resume yet, but I could see that not being something that is too far off.


Hopefully you feel my write up and experience was worth the effort that Element 14, Avnet and Xilinx put into offering this project.


On another note, I did actually complete the res of the software labs. I found them very difficult to blog about. It was a lot of typing and data entry, it doesn't make for an exciting blog, but all of the experience led to me being able to complete what I did in this final project. I hope those of you that followed my progress enjoyed what you read.