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Path to Programmable

10 Posts authored by: hans_ober
Continuing (off the course of the syllabus) from where Path to Programmable Blog 7 - Trying out a PL-only VGA design left off, I decided to try generating a HDMI/DVI video signal.   HDMI/DVI 101   VGA is an analog signal, where different voltages (from 0 to 0.7V) correspond to different intensities of color. Three wires (channels) are used to transmit R,G & B, and two 'sync' (HSYNC & VSYNC) are level triggered signals that control the scanning i.e. help the receiver determine ...
The videos & labs in Path to Programmable Blog 8 - Developing Zynq Software provided a brief intro to the software development workflow using Xilinx SDK. We now move on to the next set of videos which go over creating applications, using the Xilinx drivers and debugging.   Chapter 4 Video - Developing Applications The video picked up from where the chapter 3 video has stopped - the examples & documentation for the drivers that Xilinx provides for the Zynq peripherals. It then moved ...
In Path to Programmable Blog 6 - Hardware Debugging & some more TCL I finished Module 1 of Path the Programmable - Developing Zynq Hardware. Module 1 was centered around designing peripherals in the PL and interfacing them with the PS using Vivado, and now we move on to the software that will run on the PS.   Module 2 - Developing Zynq Software   Chapter 1 Video - Zynq System Architecture Basics  The introductory video went over the overall flow of software development for Z ...
  I tried out a couple of things that weren't a part of the Path to Programmable Course Syllabus, but I thought I'd share them: How to setup the clocks for PL-only designs with the MiniZed 3-bit VGA output from the MiniZed without a PMOD.   MiniZed Clocking  As far as trial runs are concerned, running a PL-only design follows the same process as Xilinx's non-SoC parts like the Spartan & Artix: instantiate all HDL source code in a top level wrapper, assign the I/O pins (con ...
In the previous blog post Path to Programmable Blog 5 - Creating Custom IP , we created custom IP which comprised of some HDL code that implemented a PWM controller, which was then connected to the AXI bus as an AXI-4 Lite Slave, allowing the PS to control the PWM controller. We also added an Integrated Logic Analyzer and JTAG-AXI core.   HW Chapter 9 video: Vivado's Hardware Manager This video went over the different debugging techniques: Although the ILA is implemented in the FPGA fabr ...
In Path to Programmable Blog 4 - Adding a PL Peripheral & using PS DMA, we added Block RAM to the PL and connected it to the PS using the AXI interface. We also looked at how we can use DMA to speed up transfers. The Block RAM was added to the PL using Xilinx's IP that is bundled with Vivado - which was automatically configured and connected. When working on custom designs, we need to generate 'IP' of our own i.e. somehow link registers/datapaths in our HDL to the AXI interface so that th ...
In the preceding posts, we had a quick look at what Zynq-7000 is (Path to Programmable Blog 1 - Getting Started), the workflow (Path to Programmable Blog 2 - Xilinx Tool Flow & Getting Started with Zynq-7000) and we configured a couple of PS peripherals and ran tests (Path to Programmable Blog 3 - PS Peripheral Configuration & TCL). Now comes the important part: making the PL talk to the PS & DRAM, which will be used in probably every design that targets Zynq.   HW Chapter 6 vi ...
Path to Programmable Blog 2 - Xilinx Tool Flow & Getting Started with Zynq-7000 was an introduction to typical Zynq workflow: first configure the hardware (PS & PL) in Vivado, and then export it to Xilinx SDK to work on the software side of things. This blog post covers the next 2 sets of videos & labs: the first set covers PS peripheral configuration & the second one is a quick look at using TCL in Vivado. HW Chapter 4 video: Peripherals, Peripherals & more Peripherals! This ...
HW Chapter 2 video: Xilinx Embedded Tool Flow The presenter first went over the different Vivado Design Suite editions: WebPACK is free and supports the common Zynq devices that are found on most development boards (7010 and 7020), and the more expensive HL System & Design editions which support additional features like Partial Reconfiguration & System Generator for DSP. The next slide summarized the typical workflow of Zynq Development. The hardware designer uses Vivado, the IP Integra ...
Introduction  Path to Programmable is a training course for Programmable SoCs, like the the Xilinx Zynq-7000 All Programmable SoC. As many others have pointed out, this isn't a typical FPGA/HDL course, since the training material focuses less on the digital design/FPGA aspect, but is more about using Xilinx tools (like IP based design etc) - many of which will be relevant for other non-SoC FPGAs in the Xilinx portfolio and some might apply only to Zynq (PS-PL interconnects etc.). In line ...