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Path to Programmable

13 Posts authored by: kk99
During roadtest of Arty S7 I have created a simple PMOD module with single segment display. So, I decided to use it with MiniZed SoC to create example application. I have a driver for single segment display written in Verilog. I used a top module to generate test pattern for this display module. ZYNQ7 processing system is required in this case in design to generate system clock used by top and display modules. Seven segment display is connected to PMOD1 connector. There are pinouts: - L15 -> ...
In this lab we are use a TCL scripts to prepare and finalize our hardware project.   We will use here a lab9.tcl script delivered in Speedway support documents. Please go to the following directory: ZynqHW/2017_4/Support_documents/Lab9/ and type source ./lab9.tcl This scripts is responsible for adding a new IP blocks do design like Wireless Manager or GPIO. It creates proper connections then regenerate the layout and perform synthesis and implementation followed by bitstream generation ...
In this lab we will learn how to use a hardware debugging interface to to perform run-time interactions with IP cores.   1. Adding a IP JTAG-AXI core to the design Please select Add IP and choose JTAG to AXI Master Core from IP catalog. After that please run connection automation. After that we could add a LED constraints to PWM_w_Int IP. Please right click on LED[0:0] pin located on the PWM_w_Int_v1.0 IP then select crate port. Now please select option Add Sources from Flow Navigat ...
In this lab we will learn how to create a custom IP, add it to the IP catalogue and use it in the design.   1. How to create a new AXI peripheral Please select from main bar option: Tools->Create and Package IP New IP. There will appear a wizard. Please select option to create a AXI4 peripheral. Enter package name, display name and description. Default interface settings are fine for this module. Press Finish. New IP will be added to IP catalog. 2. Modify the new IP Proj ...
In this lab we will enable PS DMA engine to improve data flow between PL-based BRAM and external DDR3 memory.   We will base on project from lab 5. We need to launch SDK. Then we need to check if in system.hdf there is present BRAM IP block. Now please create a new application project with empty application. Then we need to import test application called: dma_test.c provided in course materials. Now we could program FPGA device and launch on hardware. There is a simple applicati ...
In this lab we will create a Block RAM in the programmable logic which can be used to buffer data going between the PS and PL.   1. How to add BRAM from IP Catalog Open block design with ZYNQ7 processing system. Choose the Add IP button on the shortcut bar of the diagram. From the IP Catalog select option AXI BRAM Controller. Double click the AXI BRAM Controller and customize IP. We need to increase Data Width to 64 bits and change Support for AXI Narrow Bursts to Manual. Then click OK ...
The lab 4 gives us basic knowledge how to use Tool Command Language commands in Vivado e.g. to create scripts which could execute several steps. Main points of this lab: - TCL commands for open/close block designs, - simple TCL commands to manipulate IP integrator block designs, - exporting a block design to TCL file.   We need to launch Vivado and and from Window menu choose option: Tcl Console. In this console we could check current working directory with command pwd. After that we c ...
The Lab 3 is continuation of previous Lab. In this part we will learn how to set up additional peripherals like QSPI, USB and SD. From the SDK point of view we will learn how to use example test applications.   First step is customization of Zynq ARM core by enabling QSPI, USB and GPIO in Vivado block design. It could be done from MIO Configuration page from ZYNQ7 PS. At the end we need to re-launch synthesis, implementation and generation of bitstream. After that we could export a hardwar ...
The main purpose of lab number 2 is configuration of the Zynq processing system to use UART peripheral to run example Hello World application.   1. Enabling and configuration of a UART peripheral The Zynq SoC has MIO pins divided into two banks: Bank 0 = MIO0-15 and Bank 1 = MIO16-53. We need to set voltage for these banks to LVCMOS 3.3V. Additionally we need to enable UART1 peripheral and map it to MIO[48:49]. To do that we need to double-click on Zynq PS. On Page called MIO Configuratio ...
The main purpose of this lab is to illustrate how to create a new Zynq project using UltraFast Design Methodology within Vivado Webpack.   Zynq Proccesing System (PS) has a configurable set of built-in peripherals and direct access to Programmable Logic (PL) that can build any custom IP. So, I we need we could create dedicated soft IP in PL and use it in PS.   1. Create a new Zynq project in Vivado Below there is gallery with step-by-step instructions how to create a new project. Ea ...
The main purpose of this laboratory is configuration of environment for the development. It based on Windows PC environment and have three main steps: - downloading and installation of Xilinx Vivado WebPACK, - downloading and installation of Tera Term, - obtaining and extracting the appropriate Speedway training files archive.   I am using Linux environment and had already installed Xilinx Vivado WebPACK in version 2018.2. I described installation process here: Xilinx Spartan-7 FPGA Mak ...
The PetaLinux provides a reference Linux distribution which is integrated and tested for Xilinx devices. This distribution includes: - boot loader, - CPU-optimized kernel, - Linux applications and libraries, - Debug, - Thread and FPU support, - Web server for easy management of network or firmware configuration.   After plug in of the micro-USB cable to the USB0JTAG/UART port on the MiniZed board we are able to login to PetaLinux. Here are serial connection parameters: - Port: COM1, ...
Today I have received package with the MiniZed Zynq development board. Here are pictures of this board: What is in the box: - two layers of protection foam, - USB2.0 to micro USB wire, - three jumpers, - safety guide and instruction, - voucher for Xilinx Software Design Tool product, - the MiniZed Zynq Development Board The board is really small. On the top of board there are: - expansion shield, - two pmod expansion, - USB to JTAG/Debug UART, - USB 2.0 host interface, - ST Mic ...