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Path to Programmable

23 Posts authored by: kk99
1. Introduction I have a really nice sensor module called GDK101 which allow to measure a gamma radiation in range up to 200 usV/h. This sensor have really simple communication interfaces: I2C or UART. There is also analog output which could be used for verifying the energy spectrum analysis of gamma photons. Below there is typical connection circuit: Sensor module has sensitive 10 PIN photodiodes and transimpedance amplifier circuit. In functional block diagram there is also comparator and p ...
kk99

[PP-21] ECG signal filtering

Posted by kk99 Jan 15, 2019
I have created with usage of FIR compiler IP a simple low pass filter. The low-pass filter is described by the formula: y(n) = 2y(n-1)-y(n-2)+x(n)-2x(n-6)+x(n-12). It has cut frequency around 11 Hz. I have used it for filtering and denoising a ECG signal. Here are example signal before and after filtering: ...
The main purpose of lab 10 and 11 is to get familiar with Xilinx libraries and Pmod (Peripheral Modules )   1. Create the application project In this part we will learn how works example application which reads and writes MAC address configuration data to/from on-board QSPI flash device. We need to create a new empty application project similar to previous laboratories. Then we need to import a source file provided with support documents. We need to modify a BSP to enable support for Xil ...
kk99

[PP-19] Lab 9 - Interrupts

Posted by kk99 Jan 12, 2019
The main purpose of this lab is to get familiar with Interrupt Service Routine. We will see how interrupts works based on example with PWM LED dimmer.   1. Create the Interrupt application project We need to create a new empty application project similar to previous laboratories. Then we need to import a source file provided with support documents. It is simple application which allow to change the brightness of LED D8 from terminal input. It handles the invalid value of brightness in ...
The main purpose of this lab is to get familiar with built-in functionality for creating a SDK project archive.   1. Create a complete SDK Project archive In SDK please choose option File -> Export. Select General -> Archive File and select Next. On next screen choose button Select All and enter name of archive. Then press Finish. In the same way we could export information about Launch Configurations or Breakpoints. 2. Importing of shared project archive To import projec ...
In this lab we will learn how create a boot image for QSPI and boot from it with usage of FSBL. We will create boot image for test peripherals application and boot it from non-volatile memory.   1. Create the QSPI boot image To create a boot image please select: Xilinx Tools -> Create Boot Image. BIF (Boot Image Format) is the input file into Bootgen that list the partitions which Bootgen is to include the image. The BIF also includes attributes for the partitions. The output format ...
First Stage Boot Loader application configures the FPGA with HW bit stream and loads operating system image or standalone image or second stage boot loader image from non-volatile memory (NAND/NOR/QSPI) to RAM and starts executing it. In this lab we will learn how to generate a FSBL application using template.   1. Generate the FSBL In SDK please choose Files -> New -> Application Project. Provide name and choose option to create a new BSP. From templates please select a Zynq FSB ...
The purpose of this lab is to upload a example application from the SDK to the hardware through a JTAG connection (This part is similar to the laboratory number two from first module). Additionally we will get familiar with software debugging.   1. Configure the SoC PL with bitstream At the beginning we need to configure a hardware and set proper boot mode. We need to enable JTAG boot. We need to enable JTAG boot. It could be done by setting dip switch to position J. Here is picture of th ...
In this lab we will learn how to add a new software application to SDK based on examples with Hello World and Memory/Peripheral tests applications.   1. Start of development based on example code Please launch Xilinx SDK and choose: File -> New -> Application Project. Please enter the project name and use exiting Standalone BSP. When you press Next you will see a list of available templates. In this lab we will use a Empty Application template. By choosing other template like: Me ...
We have received a materials for second module of Path to Programmable training. Here is agenda for the second module: In my opinion first three chapters from second module  covers the same material from first module. These three laboratories contain basic information about  Zynq architecture and Xilinx SDK. So, I will start second module from laboratory number four where we will learn more information about application development. ...
During roadtest of Arty S7 I have created a simple PMOD module with single segment display. So, I decided to use it with MiniZed SoC to create example application. I have a driver for single segment display written in Verilog. I used a top module to generate test pattern for this display module. ZYNQ7 processing system is required in this case in design to generate system clock used by top and display modules. Seven segment display is connected to PMOD1 connector. There are pinouts: - L15 -> ...
In this lab we are use a TCL scripts to prepare and finalize our hardware project.   We will use here a lab9.tcl script delivered in Speedway support documents. Please go to the following directory: ZynqHW/2017_4/Support_documents/Lab9/ and type source ./lab9.tcl This scripts is responsible for adding a new IP blocks do design like Wireless Manager or GPIO. It creates proper connections then regenerate the layout and perform synthesis and implementation followed by bitstream generation ...
In this lab we will learn how to use a hardware debugging interface to to perform run-time interactions with IP cores.   1. Adding a IP JTAG-AXI core to the design Please select Add IP and choose JTAG to AXI Master Core from IP catalog. After that please run connection automation. After that we could add a LED constraints to PWM_w_Int IP. Please right click on LED[0:0] pin located on the PWM_w_Int_v1.0 IP then select crate port. Now please select option Add Sources from Flow Navigat ...
In this lab we will learn how to create a custom IP, add it to the IP catalogue and use it in the design.   1. How to create a new AXI peripheral Please select from main bar option: Tools->Create and Package IP New IP. There will appear a wizard. Please select option to create a AXI4 peripheral. Enter package name, display name and description. Default interface settings are fine for this module. Press Finish. New IP will be added to IP catalog. 2. Modify the new IP Proj ...
In this lab we will enable PS DMA engine to improve data flow between PL-based BRAM and external DDR3 memory.   We will base on project from lab 5. We need to launch SDK. Then we need to check if in system.hdf there is present BRAM IP block. Now please create a new application project with empty application. Then we need to import test application called: dma_test.c provided in course materials. Now we could program FPGA device and launch on hardware. There is a simple applicati ...