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Path to Programmable

9 Posts authored by: mconners Top Member
The first few labs in the SW Module are mostly a more in depth look at the SDK product provided with the Vivado Suite.   Lab 0 covers installing all the required tools. All of these steps were completed as part of the first set of labs, so there really wasn't anything to do.   They discuss the fact that the Editor is based on Eclipse IDE.   In Lab 1 they go into depth regarding the file we exported at the end of Lab 9 in the HW module. Z_system_wrapper.hdf. They explain that th ...
You may remember when we left off, we removed the JTAG interface from our board design, but we left the PWM module and the Logic Analyzer, so the Block Design looked like this:     and I said something about next lab we would do some more TCL scripting and I guessed it would be about removing some IP that we added. BOY WAS I EVER WRONG.   They had us open Vivado, go to the TCL console, change directories into the support directory for lab 9 and type:   source ./lab9.tcl ...
We left off last time after creating new IP and adding some debug ports. We added a PWM module, a logic analyzer, and a JTAG port.     This week we got to exercise those pieces.   First thing we did was export the hardware to the SDK workspace and created an empty application.     So we created the LED_Dimmer_Int program. We just added existing source from the provided source files directory. You might be able to make out the PWMIsr method there. This is a console ...
So far this has been the most challenging lab, mostly because of the amount of typing. We added a PWM module with an interrupt. If you've been following along, you'll see that during this lab we added the portion outlined in red.         So we added the PWM module that we created, a Logic Analyzer from the built in IP, and a JTAG interface, also from the built in IP.   As you start to go through the process of creating the new IP, you are asked a few questions, and u ...
mconners

Labs 5 & 6

Posted by mconners Top Member Nov 3, 2018
Finally starting to access the PL   I grouped labs 5 & 6 together because they really are 2 parts of a single lab. Lab 5 was adding a Block Ram to the Processing System using the AXI Interconnect System, Lab 6 was actually Programming the FPGA to create the IP, and the second half was compiling a program and installing it on the CPU to execute some DMA tests, record the timings, and calculate the speed savings using Interrupt DMA. One of the enlightening things about this lab was seein ...
mconners

Lab 4 - TCL me Xilinx

Posted by mconners Top Member Oct 25, 2018
Lab 4 - Using TCL in Vivado Embedded Designs   This lab was pretty simple, the goal was to exercise the Vivado environment via the command line using TCL. TCL is the Tool Command Language. It was invented by John Ousterhout at UC Berkeley in 1998. It was intended to unify command languages. It grew in popularity when it was adopted by Sun Microsystems. I remember hearing about TCL and TK in the nineties as a way to add GUI functionality to command line programs. That kind of seems what the ...
Overview :   This lab is similar to the previous lab, we configured some additional peripherals, export to the SDK, and exercise the newly created peripherals.       Notice in the above diagram, there are checks next to UART 1, GPIO, SD 1, USB 0,  and QUAD SPI. One of the important lessons they wanted us to learn in this lab was why the order in which you map peripherals matters. The devices are listed in priority in the green boxes above, with the memory devices ha ...
mconners

Finally got the Board

Posted by mconners Top Member Oct 14, 2018
OK, the board finally arrived, although a day later than expected, due to Hurricane Michael, fortunately the storm hit quite a bit to the west of me, so I am not dealing with hurricane aftermath.       This was a nice little guide to the board that was inside the package.   Lab exercise:   The first lab exercises mostly revolved around getting familiar with the vivado tools, as well a a customized version of Eclipse. We were brought into a Block Design configuration ...
Ok. This post won't be all that exciting. I received an email from Randall with the instructions to download the Training modules. Haven't received the hardware yet, but I figured I could at least get my dev environment set up.     I downloaded a zip file, extracted it and found a directory laid out like this:     I went into the Lab_instructions directory, and found the following     I opened up the file named ZynqHW_2017_4_lab_0_v7.pdf and it was as I suspe ...