One common question about Ultra96-V2 is regarding the exact differences in the Micron LPDDR4 with Ultra96-V1. The V1 had a dual-die device which is now EOL. The V2 has an updated, single-die device with the exact same capacity and timing parameters. However, the difference in die quantity shows up as a Rank and Addressing change in the ZU+ PS DDR controller parameters, which affects the designs at the FSBL level.


These are the MPSoC PS DDR controller differences on the Ultra96-V2’s Micron LPDDR4 (MT53D512M32D2DS-053 AIT:D) compared to Ultra96-V1's LPDDR4 (MT53B512M32D2NP-062 WT:C).


<user_parameter name="CONFIG.PSU__DDRC__DEVICE_CAPACITY" value="16384 MBits"/>

<user_parameter name="CONFIG.PSU__DDRC__RANK_ADDR_COUNT" value="0"/>

<user_parameter name="CONFIG.PSU__DDRC__ROW_ADDR_COUNT" value="16"/>


And here is how that looks in Vivado:

Vivado Block Design PS DDR Controller Settings for Ultra96-V2


The other key differences are the speed grade and temperature grade. The V2's LPDDR4 speed-grade is faster, but that is irrelevant since the LPDDR4 interface is limited by the MPSoC package. The faster speed-grade was selected based on availability. Additionally, the temperature grade for the LPDDR4 on the V2 is I-grade, making it possible for us to release an I-grade temp Ultra96-V2, which we are working towards for the Fall 2019.