A VCU-based design example is now available for the UltraZED-EV SOM and Carrier Card.


The VCU implementation was ported from the Xilinx v2018.3 ZCU106 VCU TRD design, so this example is setup (architecturally) to be extended to incorporate the other TRD design module capabilities.


If you just want to dive in, jump straight to the release and test notes in the repository:

    • A Petalinux v2018.3 BSP
    • Pre-built SD-Card images (for booting from microSD)
    • Instructions for testing the design on the UZ7EV SOM with Carrier Card
    • Documentation of the porting process used to generate this design
  • Testing the Design:Design Testing on the UltraZED-EV + Carrier Card
    The Test Notes contain instructions for configuring and using the major design features under Linux from the Gstreamer Framework, including:
    • Configuring and Working with the DisplayPort Interface
    • Testing the VCU Decoder with local playback
    • Configuring and Working with a USB Webcam with local preview
    • Testing the VCU Encoder with local playback and network streaming (RTP/UDP)


Design information:

Base v2018.3 Vivado+Petalinux Design with:

  • LEDs, DIP Switches, Pushbuttons
  • DisplayPort, USB Host/Device Support, Console UART
  • VCU Support (H.264, H.265, Encoder/Decoder)
  • GStreamer / V4L2 framework and tools


If you want to grab a copy of the repository, clone it locally:

$ git clone https://xterra2.avnet.com/xilinx/zedboard/ultrazed-ev/avnet-uzev-ports.git
Cloning into 'avnet-uzev-ports'...
remote: Enumerating objects: 236, done.
remote: Counting objects: 100% (236/236), done.
remote: Compressing objects: 100% (145/145), done.
remote: Total 236 (delta 96), reused 189 (delta 77)
Receiving objects: 100% (236/236), 261.55 MiB | 14.81 MiB/s, done.
Resolving deltas: 100% (96/96), done.


See the README.md file In the ./rdf0428-uz7ev-vcu-trd-2018-3/pl/ folder for information on using the Vivado TCL scripts to generate the VCU design.


A quick architectural overview:


The MPSOC Subsystem design:

MPSOC Subsystem Block Diagram

  • MPSOC AXI Connections from the ZCU106 VCU TRD Design
    • AXI High Performance (non coherent) connections for
      • VCU Encoder data (S_HP2)
      • VCU Decoder data (S_HP3)
      • AXI Interconnect Block (M_HPM0)
    • AXI High Performance (coherent) connections for
      • VCU MCU (S_HPC0)
  • AXI Interconnect Block Connections from the ZCU106 VCU TRD
    • IRQ Generation (M04)
    • VCU (M08)
  • AXI Interconnect Block Connections from the UZ Petalinux design
    • On-board DIP Switches (M00)
    • On-board LEDs (M01)
    • On-board Pushbutton Switches (M02)


The Top Level Design:

Top Level VCU Design Block Diagram

  • PL blocks from the ZCU106 VCU TRD Design
    • 3 x AXI Interconnect Blocks for
      • VCU Encoder
      • VCU Decoder
      • VCU MCU
    • 1 x Reset Slice for GPIO-based VCU Reset
    • 1 x Concat block for IRQ routing
    • 1 x Clock Wizard Block for
      • Generating the VCU Clock
      • Generating the High Speed AXI bus clock (VCU and Display Related)
  • PL blocks from the UZ Petalinux Design
    • 3 x AXI GPIO blocks for
      • On-board DIP Switches
      • On-board LEDs
      • On-board Pushbutton Switches