• Problem with interrupts with EMIO

    Hello everyone, recently I obtained a Zedboard and I downloaded this document from Xilinx: Zynq-7000 SoC: Embedded Design Tutorial from this link: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_2/u...
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    created by torjaquintero
  • Difficulty booting Ubuntu on Aedboard

    Hi, I currently have difficulty in getting Ubuntu running on my zedboard. I am using the tutorial 'Zedboard Ubuntu, Vivado 2013.4' which I obtained from | Zedboard . I'm using Vivado 2013.4 as well as CentOS8 as my Vi...
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    last modified by vivekgov
  • Zedboard for sale

    Hi guys hope.you are all well. I have several of these zedboard available for sale. Brand new sealed with the liscence and software for £150 gbp price includes delivery. Payments is through paypal so safe for bot...
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    last modified by theduke
  • Need Zedboard source code to drive outputs that test Maxim MAX11198 Eval kit

    Hi,   I have a customer interested in this kit to evaluate a MAX11198 device:   https://datasheets.maximintegrated.com/en/ds/MAX11198EVKIT.pdf   This is an FMC card and in the description, it says th...
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  • *.xdc file, Zynq 7000 Epp, 7Z020 CLG 484-1 Zedboard upload

    I own an Digilent Avnet Zedboard (Zynq 7000 EPP, 7Z020 CLG 484-1, Revision D). This is an older version of the zedboard.    Can anyone upload the master *.XDC file for this specific board? I looked at t...
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  • Hi how can I view a zedboard output in CRO?

    Hi how can I view a zedboard output in CRO?
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  • Super new to FPGAs but a friend just bought me a ZedBoard Zync-7000; obviously I can do a lot, but where should I start?

    I'm almost done with my first ever CS/CE class (basically an introduction to digital electronics). I've gone over basic stuff like Karnaugh maps, adders, muxes, and decoders, and I know a bit of verilog, both for runn...
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    last modified by olympiapeter
  • Debugging with ILA Core

    Hello,   I am a total beginner wit fpga, and the last few das, I've been fiddling with the ZedBoard, and following some exercices on how to program the PL.   The current exercise consist of adding a binary...
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    last modified by blelly_pie
  • DDR3 address/command /control termination on board

    Hello, Why in the Z-Turn/PicoZed/MicroZed/ZedBoard there are always 40.2 ohm termination resistors for address/command/control of the DDR3 ? Why the ODT (on-die termination) available in the memory chip is not used ?...
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    last modified by lucatesta
  • Build me an Embedded Processing System and I'll Give You a Zynq®-7000 SoC ZC702 Evaluation Kit

    I was in the right place at the right time. I was asked, "I have two Zynq®-7000 SoC ZC702 Evaluation Kits, would you like them?" For one second I paused, and declared," YES!" So, here I am, sitting at my desk ...
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    created by pchan
  • Does the FMC header support 1.8V or 2.5V?

    I see the FMC header is connected to bank 34/35, and I understand those banks are designated as HP, meaning they do not support LVDS_18 -   I also see that the Vadj jumper can be set to 1.8V. What would happen ...
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  • Creating hardware based off of ZedBoard, which portions of the ZedBoard schematic do I need?

    I need a few things. I will reference pages from the ZedBoard Rev D.2 schematic.   One, I the programming interface to the SoC via USB. I believe that this is covered on page 12. I also need the ability to inte...
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  • Zedboard Progrming with JTAG(alone) Using Xilinx-14.2

    Hi.........   I new to zedboard(XC7Z020).I want to dump the VHDL/Verilog codes into the fpga through JTAG(Impact tool),So can i program the fpga through JTAG(alone) or we need Kernal code in SD code to program th...
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    last modified by satish.84ts
  • kgdbwait parameter is not waiting while booting the board

    Hi,    I have enabled the KGDB for kernel debugging through serial in kernel config and passing the below arguments in kernel parameter, but kernel is not waiting for GDB to debug. Kernel arguments: setenv...
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  • display an image on the computer from the Zedboard's BRAM

    Hello, I have an image stored on the the Zedboard's BRAM , I want to display on the computer's monitor. Regards
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    last modified by mariem_@fsm.12-34

    Hi everyone,     I would like to redirect Ethernet payload comming/going from/to Eth0 port on zedboard without requiring intervention from PS (although it can provide initial configurations). In other wor...
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    last modified by joaoamraal
  • JC and JD PMOD Resistors for Single-Ended

    Hey, Sorry to beat a (few) dead horses [1] [2] [3] but would like a bit of clarification on using the Differential JC/JD PMOD's for single-ended mode. In the linked posts it has been claimed that it can be done...
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    last modified by minersrevolt
  • How to add IP in Block Design

    Quick quesiton, hopefully simple. I'm trying to integreate a Multiplier IP block into the block design shown on page 12 of this tutorial: http://ece-research.unm.edu/jimp/codesign/Vivado/VivadoHelloWorldTutorial.pdf ...
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    last modified by cannadya1
  • Transfferring data from PS to PL

    I am using Zynq7000. I have my data in the Processor System (PS) obtained from the PC through UART and stored into an array. How can I transfer these data from the PS to the FPGA (PL)? I saw some resources only said t...
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    last modified by kinyau94
  • ZedBoard HDMI VIPP, Vivado 2014

    Hi I am trying to use the ZedBoard_HDMI_Display_Tutorial_2013_4_20140623.zip that I downloaded from Zedboard reference design forum at: ZedBoard HDMI VIPP, Vivado 2014. http://zedboard.org/support/design/1521/1...
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