• *.xdc file, Zynq 7000 Epp, 7Z020 CLG 484-1 Zedboard upload

    I own an Digilent Avnet Zedboard (Zynq 7000 EPP, 7Z020 CLG 484-1, Revision D). This is an older version of the zedboard.    Can anyone upload the master *.XDC file for this specific board? I looked at t...
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  • Hi how can I view a zedboard output in CRO?

    Hi how can I view a zedboard output in CRO?
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  • Super new to FPGAs but a friend just bought me a ZedBoard Zync-7000; obviously I can do a lot, but where should I start?

    I'm almost done with my first ever CS/CE class (basically an introduction to digital electronics). I've gone over basic stuff like Karnaugh maps, adders, muxes, and decoders, and I know a bit of verilog, both for runn...
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  • Debugging with ILA Core

    Hello,   I am a total beginner wit fpga, and the last few das, I've been fiddling with the ZedBoard, and following some exercices on how to program the PL.   The current exercise consist of adding a binary...
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  • DDR3 address/command /control termination on board

    Hello, Why in the Z-Turn/PicoZed/MicroZed/ZedBoard there are always 40.2 ohm termination resistors for address/command/control of the DDR3 ? Why the ODT (on-die termination) available in the memory chip is not used ?...
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  • Build me an Embedded Processing System and I'll Give You a Zynq®-7000 SoC ZC702 Evaluation Kit

    I was in the right place at the right time. I was asked, "I have two Zynq®-7000 SoC ZC702 Evaluation Kits, would you like them?" For one second I paused, and declared," YES!" So, here I am, sitting at my desk ...
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  • Does the FMC header support 1.8V or 2.5V?

    I see the FMC header is connected to bank 34/35, and I understand those banks are designated as HP, meaning they do not support LVDS_18 -   I also see that the Vadj jumper can be set to 1.8V. What would happen ...
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  • Creating hardware based off of ZedBoard, which portions of the ZedBoard schematic do I need?

    I need a few things. I will reference pages from the ZedBoard Rev D.2 schematic.   One, I the programming interface to the SoC via USB. I believe that this is covered on page 12. I also need the ability to inte...
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  • Zedboard Progrming with JTAG(alone) Using Xilinx-14.2

    Hi.........   I new to zedboard(XC7Z020).I want to dump the VHDL/Verilog codes into the fpga through JTAG(Impact tool),So can i program the fpga through JTAG(alone) or we need Kernal code in SD code to program th...
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  • kgdbwait parameter is not waiting while booting the board

    Hi,    I have enabled the KGDB for kernel debugging through serial in kernel config and passing the below arguments in kernel parameter, but kernel is not waiting for GDB to debug. Kernel arguments: setenv...
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  • display an image on the computer from the Zedboard's BRAM

    Hello, I have an image stored on the the Zedboard's BRAM , I want to display on the computer's monitor. Regards
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    Hi everyone,     I would like to redirect Ethernet payload comming/going from/to Eth0 port on zedboard without requiring intervention from PS (although it can provide initial configurations). In other wor...
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  • JC and JD PMOD Resistors for Single-Ended

    Hey, Sorry to beat a (few) dead horses [1] [2] [3] but would like a bit of clarification on using the Differential JC/JD PMOD's for single-ended mode. In the linked posts it has been claimed that it can be done...
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  • How to add IP in Block Design

    Quick quesiton, hopefully simple. I'm trying to integreate a Multiplier IP block into the block design shown on page 12 of this tutorial: http://ece-research.unm.edu/jimp/codesign/Vivado/VivadoHelloWorldTutorial.pdf ...
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  • Transfferring data from PS to PL

    I am using Zynq7000. I have my data in the Processor System (PS) obtained from the PC through UART and stored into an array. How can I transfer these data from the PS to the FPGA (PL)? I saw some resources only said t...
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  • ZedBoard HDMI VIPP, Vivado 2014

    Hi I am trying to use the ZedBoard_HDMI_Display_Tutorial_2013_4_20140623.zip that I downloaded from Zedboard reference design forum at: ZedBoard HDMI VIPP, Vivado 2014. http://zedboard.org/support/design/1521/1...
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  • Partial Reconfiguration using ICAP and AXI DMA

    Hello I'm using a ZYNQ Zedboard development board. I'm studying the Partial Reconfiguration using ICAP. I implemented a system with Zynq Processing Unit, ICAP and AXI DMA. The DMA accesses to the memory and transfers ...
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  • ZedBoard_OOB_Design 

    ZedBoard_OOB_Design  offers us a hardware project  xps_proj.I want to design a vdma image processing .So i add xapp1167 demo's hls ip and a vdma ip  to xps_proj.But  xps can't genera...
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  • device tree generation

    Dear Sir,               I am following the scripts at  http://microzed.org/product/wilink-8-adaptor. I am trying to integrate the Wilink8 WiFi...
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  • HDMI in and out on Zedboard

    I am using the Xilinx Inreuvium daughter card which to connect a hdmi source and a monitor to the zedboard. I am suspecting that the traces from the daughter card to the FPGA on the zedboard are not controlled and one...
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