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The following workshop is now available for On-Demand Viewing:


In this seminar series, we’ll explore how Xilinx FPGAs and SoC’s mitigate common challenges engineers encounter when building embedded designs. You’ll discover Xilinx’s embedded solutions options as well as diverse IP library, including partner IP,  that enables anyone to build a complete and custom embedded solutions.


We’ll walk through the steps getting started using Xilinx design tools to build a custom microcontroller from installing the design tools to communicating with an external sensor. And you’ll find out that this is easier than ever and anyone can do this!


You can view Part 2 and Part 3 of this workshop below:


Also, check out the Arty-S7 round up here:




Survey Results:


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Q&A Session:


Is possible to perform workshop labs using the arty-z7 20?


You might be able to.  It is recommended to use the device in the lab as that is what we have tested.  With a smaller part, you might run out of resources or you might run into other unintended issues.  Off the top of my head, there is nothing in there that you MUST target a 50 size, but I cannot tell you it actually will work as we have not tested that. For this course, we have reduced the cost of the Arty S7 50 board.  You will need access to PMODs as well.


Is the Dual 12-bit ADC you are referring to is connected via XADC?


the built in ADC is the XADC


Are there plans to move from the ARM-A9 to ARM-A35 for better performance, power power, and 64Bit and keeping cost down?


Are you referring to the Microblaze, or are you referring to the SoC product line?  Overall, Xilinx has moved from A9's to A53s in their product lines for their SoC products (if that was the question)


is the microblaze good for production as well, or is it for designing the product easily and then later on replace the fpga peripherals with actual hardware? (sorry, i'm relatively new to fpga)


yes, it has been used in production for a very long time (think decade time-frame - I cannot recall the timeframe, but VERY long time).  As it is a soft core, the same core has been revised, and updated and enhanced over that time.  In FPGAs, this is actual hardware.  You assign gates / hardware to behave as you decide.  The point is not to simulate a core, then replace with a separate chip...the idea is you can put down what you think you need and then add / enhance later as needed.


what is the difference between MicroBlaze and MicroBlaze MCS?


Microblaze is the softcore, and Microblaze MCS is an entire micro controller system, which includes the softcore itself


is microblaze support linux, if so how about speed & flash memory requirement.


Yes, Microblaze supports Linux.  The clock speed is selectable, and the flash requirements depend on your solution.  I am sorry, I do not think I can be more specific in a 1 sentence reply.  There are user guides on this and you can play around with the options in the tools if you need more details.


I am trying to communicate a Zynq board to a real time simulator as a device under test for HIL testing, and I need to know how to do that.


You should post this question to the E14 support forums if it is a Designed by Avnet board.  Otherwise, please post to the Xilinx support forums.


Hello. Are there any plans to have some of the low-end FPGAs (e.g. Spartan, Artix) with one or more hard-core microcontroller cores as PS? (MB or ARM).


Those exist in the Zynq-7000 SoC family.  There are single or dual core versions.  There is also the MPSoC family that has dual R5 and quad A53's.  Or did you mean something different?


Can we use 2019.1?


no, there are features we will be using that are part of the 2020.1 tools..


I have Vitis 2019.2 installed. Does it work for this workshop?


We recommend you to use Vivado 2020.1 and Vitis 2020.1 to follow up with the labs


SoC product, the main issue is the MPSOC is very $$$ Looking just for more ARM Cortex processing resources


I am unaware of this, but the MPSoC has R5's and A53's.  You can add the softcores into SoC's as well to tune your processing needs


How to update boards on ver. 2018


This is not available in 2018 tools.  It is a new feature in the newer tools.  You will need to update to the 2020.1 tools if you want to follow this labs.


I was thinking more on microcontroller cores like Cortex-M series. As an example the Smartfusion2 from Microsemi/Microchip


I am unaware of any plans to add hard core Cortex-M type devices due to the capability to add the softcores to devices..


How to update to 2020 from 2018. Where is update option ?


You have to download the install package and install accepting the licenses due to the import/export restrictions.


But in this case I will have two version of Vivado ! Should I then deinstall 2018 ?


No you shouldn't uninstall 2018, You can download 2020.1 and this won't affect 2018 version


Is the tool free of charge for a single user?


depending on the devices you are working with, yes


Can you tell What is the processor which uses minimum resources that can run on arty S7?


you can tune the processors and the resources used varies depending on the options you choose.  When you select the softcores, you can tune those resources


Why should I accelerate with hardware using FPGA rather that GPU?


that is a question that is hard to answer in one webinar single answer, but the processing power per watt is higher and you get to create and tune the accelerator to your custom needs .


Jayson mentionned some other tool for CPU development (I didn't catch the exact name), but it wasn't SDK, but some other name ... ATIS or something like that


thank you for clarifying, 2020 uses it's own built in capabilities.  What Jayson mentioned, was an external tool supported by the ARM flow.  That is called Keil


apparently state machines are some sort of war stories passed around to fellow fpga designers :P


yes...they are.  I designed on a FPGA once where I had to re-write the state machine 3 times as it did not work properly (note, this was NOT a Xilinx FPGA)


In 2018 I used Xilinx SDK for developing ARM/Microblaze code. Is SDK still valid for 2020 ?


SDK is now inside Vitis


Ok I reminded. It was Vitis. Is it something similar to SDK ?


It is still the same Eclipse interface and for the most part the same overall, but it has a lot of enhancements to integrate with other capabilities that Vitis provides


That is where I had problem, is the platform generation


Key is platform generation as well.  I am the Avnet architect of our platforms and once they are set properly they are fantastic!


Can you run Zynq without external memory if using mostly PL


it is difficult, but yes, we do have customers doing this


Im new to FPGAs, last year while debugging a nasty bug I after lots of hours spent debugging I found that Xilinx simulator and compiler interpret Verilog code differently. Does Xilinx have plans to parse them with the same code in the future?


They should not be interpreting the code differently.  There are pieces of simulation code that are NOT interpreted by hardware, but that is industry standard "simulation only" code.  Maybe that is what you are referring to?


How easy will it be to use the Digilent Arty board to run the examples?


You will get to experience how easy it is in the next couple of sessions. It's a plug and play


No, configuration memory, i.e. bitstream


Which device?  Different devices access this memory differently