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The following workshop is now available for On-Demand Viewing:

 

In this seminar series, we’ll explore how Xilinx FPGAs and SoC’s mitigate common challenges engineers encounter when building embedded designs. You’ll discover Xilinx’s embedded solutions options as well as diverse IP library, including partner IP,  that enables anyone to build a complete and custom embedded solutions.

 

We’ll walk through the steps getting started using Xilinx design tools to build a custom microcontroller from installing the design tools to communicating with an external sensor. And you’ll find out that this is easier than ever and anyone can do this!

 

You can view Part 1 On Demand below:

 

 

You can view Part 2 and Part 3 of this workshop below:

 


Also, check out the Arty-S7 round up here:

 

 

Survey Results:

 

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Q&A Session:

 

I've just installed Vivado on Ubuntu. How to configure it ? Launch tool "vivado" isn't visible out of installing directory

 

Installing Vivado doesn't always install an icon on the Ubuntu desktop.  You can always start Vivado via the Linux command line: $ vivado &

 

I can launch only when I go to installing directory, i.e. /toolsTXilinx/Vivado/2020.1/bin.  

 

You can launch Vivado from anywhere, but you have to first run the script to set some required environment variables: $ source /tools/Xilinx/Vivado/$TOOLS_VER/settings64.sh $ vivado &

 

How to launch from home folder ?

 

$ source /tools/Xilinx/Vivado/$TOOLS_VER/settings64.sh $ vivado &

 

is there a guide for creating a project using tcl?  For example, the example project use tcl to create the project?

 

Xilinx UG835 and UG894 are good resources for using TCL to create projects in Vivado

 

what is the difference between MicroBlaze and MicroBlaze MCS?

 

Microcontroller preset suitable for microcontroller designs. Area optimized, with no caches and debug enabled.

 

i cannot see in vendors digilentic.com

 

This step was done in Lab. In Vivado 2020.1 open Tools> XHUB Stores then in boards download Arty S7-50 from Digilent Inc

 

If you change the PLL clock output (wizard)  from 100 to 150 will the design be updated?

 

Yes, that change should propogate to the rest of the design.

 

how can you add one more GPIO to a pin on the same GPIO controller?  The issue I have is how to add a net to an array

 

You can configure the axi_gpio i/o port to be 1-32 bits, and each axi_gpio supports to 'channels'.  The channels can be configured to be output-only, input-only, or input-output.

 

Is there an easy way to rename a project and its subsequent directories using a TCL command(s)? The reason is to reuse a certain baseline Vivado project to create variations of the same baseline SoC. By just copying and renaming a baseline project we can avoid recreating it from scratch

 

You can export your project to a TCL file, and then edit that TCL file to change the project name, etc..

 

how do you wrtie the C code eclipse?

 

I believe that is coming in the next episode.  Stay tuned!

 

How to define peripheral registers

 

This can be done through shared memory

 

Can you provide a linki for C code examples for the microblaze?

 

The Vitis tool provides code for some sample applications.

 

What do you recommend to do if you have more then 16 ip connected to the axi_periph ip?

 

You can cascade an additional Interconnect IP downstream -- https://usermanual.wiki/Document/ug1037vivadoaxireferenceguide.1957650522/html#pf27

 

can you change the address locations?

 

Yes, you can edit the address map for the peripherals.

 

When I started bitstream generation, Vivado suddenly crashed

 

Can you report this issue through Xilinx Forums: https://forums.xilinx.com and we will be able to report an issue if it was reproducible at our end. Thanks!

 

How do I assign clock, uart, spi lines to correct pins at boards which are not known to Vivado.

 

You can manually add external ports to the block design, and then add the location constraints for those port pins to the XDC constraints file.

 

How we go about connecting the UART to GPIO pins instead of the USB UART board connection?

 

You can create the external Rx & Tx UART ports manually and connect them to your UART.

 

what is difference between intel and xilinx fpga

 

They may share the same processor but they are different in the peripherals and architecture.

 

aside from the complexity of the design, what determines the speed at which the bitstream is built? the type of ip used for example? i guess the speed of your computer? would the type of target fpga also make a difference?

 

Lots of factors influence how quickly a design will build.  PC resources (CPU freq, number of CPU cores, amount of RAM (more is always better!)) are key.  The size of the target FPGA device also matters.  Designs for smaller FPGAs will build faster than designs targeting larger FPGAs (and have different PC memory requirements for Vivado).

 

how can we see the content of the xsa file?

 

You can rename the .xsa file to .tar.gz (I think) and then open it in your favorite archiver tool (7-zip, winzip, etc.)  Generally speaking this is not necessary, and you don't want to change anything in the .xsa file.

 

Where we can find firmware code examples on how to initialize and use certain AXI-based peripherals (interrupt controller, timers, SPI, I2C, UART) with the Microblaze CPU?

 

You can dig into the driver sources for the peripherals in Vitis when are working on yoru software.  That will give you an idea how the peripherals are initialized, etc.

 

What about the lights and buttons?

 

This can be used for the bonus part as Jayson described in slide 62

 

We have just overwritten the pre-installed firmware.  How can we restore the original code?

 

The original Out-of-box image for the Arty-S7 is available on the Digilent website. If you use JTAG for configuration, you are not overwriting the non-volatile memory, so that code will still be there.

 

program fpga, does that only program the bitstream? when is the application loaded?

 

Program FPGA just configures the FPGA.  The application is loaded after the FPGA is configured.