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The following workshop is now available for On-Demand Viewing:

 

In this seminar series, we’ll explore how Xilinx FPGAs and SoC’s mitigate common challenges engineers encounter when building embedded designs. You’ll discover Xilinx’s embedded solutions options as well as diverse IP library, including partner IP,  that enables anyone to build a complete and custom embedded solutions.

 

We’ll walk through the steps getting started using Xilinx design tools to build a custom microcontroller from installing the design tools to communicating with an external sensor. And you’ll find out that this is easier than ever and anyone can do this!

 

You can view Part 1 and Part 2 On Demand below:

 

 

Also, check out the Arty-S7 round up here:

 

 

Survey Results:

 

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Q&A Session:

 

128 memory holds program memory?

 

Yes, the 128 memory is large enough, and the software here for this example is small enough, that it fits in the block RAM (BRAM) attached to the MicroBlaze.

 

Are there any good tutorials showing how to create a board support package for a custom board we might develop? I am thinking of having the kind of support like the Arty S7 On the same note, any good examples on how to create support for an add-on board like the P-mods?

 

If you are referring to the Board Definition that gives Vivado "Board Awareness" of the Arty-S7, then you can refer to Appendix A of https://www.xilinx.com/support/documentation/sw_manuals/xilinx2020_1/ug895-vivado-system-level-design-entry.pdf

 

 

Are there any good tutorials showing how to create a board support package for a custom board we might develop? I am thinking of having the kind of support like the Arty S7 On the same note, any good examples on how to create support for an add-on board like the P-mods?

 

If you use our Xilinx IP, or partner IP, we auto create the BSP for you!!!!!!  BSP is simply a collection of drivers.  And we have drivers for all our IP, for both BareMetal and Linux If you build your own custom IP, you must make your own driver, but most simply leverage existing drivers

 

Wouldn't it be better to connect the PNAV to the PMOD connector C or D, since they use a 200 ohm resistor (that would protect the FPGA in case one makes a mistake)?

 

That's fine too

 

why is the constraint file not needed ? or is it used but we dont see it.

 

the tool is smart enough to pull in the constraints and generate the timing needs based on the clocks attached to the various IP

 

What is the difference between interrupt handling (in uBlaze) and exception handling (in Zynq)? What is the significance of exception particularly?

 

Interrupt handling and exception handling are not the same thing.  MicroBlaze also has a configurable exception handler.  This is used by software (operating system) to detect and gracefully handle issues before they crash the system.  An interrupt handler is a software routine to do something specific when the interrupt signal goes active.

 

how do i make my bitstream survive a power cycle? i noticed the board always resets to the default demo after a power cycle

 

The FPGA is SRAM based.  the default demo is being reloaded at each power cycle.  You would need to load your image into the flash space so that it is loaded instead.

 

Do we have to time constraint any internally generated clocks, say for output SPI clock of the SPI interface or any internal reference clock?

 

No, the tool handles that.  Typically you only have to handle exceptions, such as external clocks feeding into the chip

 

once the bsp has been generated and used in vitis, what if we add IP? does the bsp get automatically updated?

 

depending on your build settings, you might have to manually tell it to rebuild, but the tool does update the BSP as you tell it to update

 

Connecting IP blocks appears to be easy as you say, but the possibilities are limited to the IPs that already exist. Could you share a link to a good resource to learn how to write our own IPs to interface the PL to the PS? (A webinar about that in the future would also be great)

 

You may want to have a look at Xilinx UG1118 (https://www.xilinx.com/support/documentation/sw_manuals/xilinx2020_1/ug1118-vivado-creating-packaging-custom-ip.pdf) and UG1119 (https://www.xilinx.com/support/documentation/sw_manuals/xilinx2020_1/ug1119-vivado-creating-packaging-ip-tutorial.pdf).

 

How to merge .bit and .elf  to a .mcs file in a uBlaze project and load from the flash memory? Do we have to add fsbl also, if so how to configure it?

 

this is part of the flow when you are working in the tool, you should see that by exporting the bit from Vivado, Vitis will already be pointing to the proper things for packaging

 

As I understand local memory is BRAM, what is it used for the cache memory? (I would expect it to be something faster than BRAM)

 

BRAM is the fastest memory.  It runs at system speed.

 

do we get the instructions how to build with ddr3?

 

Yes, I will send out after this presentation

 

 

Download solutions for this workshop here:  http://avnet.me/arty_s7-50_mblz_soln