I would love to see a TIS-100 inspired physical machine:
* A small display over each of the nine cores to show the code.
* A larger display to show the input stack and outputs.
* The ability to reprogram the cores.
* Indicators to show IO between the cores and if the core is blocked
* Ability to feed external data to at least one of the cores
* Ability to output data externally
If you don't have interest in making one of these some advice about the chips you would use for the cores would be handy.
Here is the command reference:
Not part of the original spec it would be cool if each chip could detach and possibly had stackable headers so you could expand the cores in any direction.