Model Composer is a Model-Based Design tool that enables rapid design exploration within the MathWorks Simulink® environment. It speeds up the path to production on Xilinx All Programmable devices through automatic code generation.
You can express and iterate through your algorithms using high-level performance-optimized blocks. You can also validate functional correctness through system-level simulations. Model Composer takes your algorithmic specifications to production-quality implementation through automatic optimizations that extends the Xilinx High Level Synthesis technology.
High-Level of Abstraction: Algorithm-centric building blocks, with a focus on functionality, provide ease-of-use essential for domain experts to accelerate design exploration.
Application-Specific Libraries: Performance-optimized Computer Vision, Math, and Linear Algebra libraries available as blocks for simulation and high-performance implementation on Xilinx All-Programmable devices.
Import synthesizable C/C++ as Custom Blocks: Ability to create your own custom blocks for simulation and code generation provides greater flexibility to design your differentiated algorithms.
Seamless Integration with Simulink: Direct connection with blocks from the Simulink product family enables system-level modeling and simulation and the ability to fully leverage the stimulus generation and data visualization capabilities of Simulink's graphical environment.
Automatic optimizations: Analyses your algorithmic specification within Simulink and performs automatic optimizations to steer towards a micro-architecture that optimizes for throughput, reduces Block RAM utilization, and enables concurrent execution of blocks.
Export to Vivado HLS: Advanced feature that provides a link between Simulink's graphical environment to design, simulate and validate your algorithms and Vivado HLS, by automatically generating everything you would need to further optimize your algorithm, including test vectors logged from simulation.
Automatic Test Bench Generation: Automatic logging of test vectors from simulation and generation of test bench to verify functional equivalence between the executable design and generated code.