The Xilinx Developer Forum (XDF) was held from October 1-2 in downtown San Jose, Ca, and featured two full days of seminars on all aspects of adaptive hardware design, as well as offering attendees a chance to talk shop with Xilinx experts and others in the Xilinx developer community. Victor Peng, President and CEO of Xilinx, opened the forum's second day with the keynote address where he introduced a new product category called, the Adaptive Computing Acceleration Platform (ACAP for short), and is key to enabling Xilinx's vision of building the "adaptable intelligent world." This blog is a summary of my notable moments and memories of XDF 2018.

 

Seminars

Both days of XDF featured breakout sessions on topics of interest to developers. Topics such as "The State of FPGA Acceleration," "The Nuts and Bolts of Computational Storage Platform," "Fundamentals of FPGA-based Acceleration," "Accelerating AI in Datacenters: Xilinx ML Suite," "AWS IoT and Xilinx," and "Video Compression: Embedded Software Strategy & Developments, an Introduction," would have appealed to just about anyone, but perhaps would have been especially useful information to those wanting a big picture or starting point.

 

But there were more than enough meaty sessions to satisfy the experienced developer, with topics such as "BigStream FPGAs: Moving Computation to the Data Center," "Xilinx Machine Learning Strategies with Deephi Tech," "Avnet System Design from Antenna to Digital with Zynq UltraScale+ RFSoC," "Empowering Software Developers - Scaling FPGA Application Development," and "NGCodec: Using High Level Synthesis and SDAccel to Develop Best in Class HEVC/VP9 Video Compression." There were also some expert panels, including "Hardware Design with Vivado," and "SDAccel." And I surely don't want to forget the "Conversation with Xilinx Research Labs."

 

The Debut of the Ultra96

This was the first XDF for Ultra96, Avnet's newly launched development board based on the Linaro 96Boards specification, which enables hardware and software developers to explore the capabilities of the Zynq® UltraScale+™ MPSoC. The Ultra96 is an entry-level Zynq UltraScale+ MPSoC development environment takes the Linaro 96Boards’ open specifications and defines a single board layout for the kinds of platforms that software platforms, hardware devices and other system developers.

 

At the Ultra96 display of the Avnet booth (pictured left) there was an endless line of attendees wanting to learn more about the Ultra96. It was really amazing to watch! I guess getting programmable logic acceleration engines on a compact board for a couple of hundred bucks is a dream come true and too good to pass up and most didn't. On day two of the forum, there was a double-wide line of folks lined up to the espresso station wanting to buy one. Not to forget: There were also a few notable breakout sessions on the Ultra96 such as "Ultra96: Software Acceleration with SDSoC Intro," "Ultra96: Using Python with Zynq SoCs, an OpenCV Example," and "Ultra96: Intro to Community Board and Xilinx Embedded software."

 

Exhibitor Booths

In addition to the meeting rooms used for the breakout sessions, there were three long hallways of exhibitor booths. Exhibitors offered great demos on their products, services and applications. Here's a taste of the companies exhibiting at XDF:

  • Bigstream Solutions, inc. has developed a hyper acceleration technology that allows Big Data platforms to be accelerated on CPUs and FPGAs.
  • BlackLynx Machine Learning uses its technology along with Xilinx® Alveo™ Data Center accelerator cards to maximize image and video analysis at the edge of the network.
  • DeePhi Technology (now part of Xilinx) provides a  Deep Neural Network Development Kit (DNNDK™) and a DeePhi™ deep learning SDK to simplify and accelerate DL applications’ development and deployment on the DeePhi DPU™ (Deep Learning Processing Unit) platform.
  • Xylon designs optimized logicBRICKS IP cores and offers design services for Xilinx FPGA and SoC/MPSoC devices.

 

Keynote Address

The ballroom was packed with people.  Everyone waited in anticipation on what Mr. Peng would say in his keynote address on the second day of XDF. The excitement and build up made you feel like something big was going to happen. When he finally came out, however,  he began his talk in a rather low-key, self-effracing manner by telling everyone a little about himself: he was a marathon runner, having participated in about 100 races. He talked about "the long distance run" a couple of times, and used this metaphor as a bridge to the long distance run of a company that is undergoing a transformation. That transformation was the focus of his speech. He mapped out Xilinx's transformation of moving beyond FPGAs. He stated, Xilinx is not an FPGA company, but a platform company. And that platform was the new product category he announced, Versal, which goes beyond FPGAs, SoCs, MPSoCs, and RFSoCs. Versal is an adaptive computing acceleration platform (ACAP).

 

More on Versal

I mentioned ACAP already. But what is it? And why is it a big deal? Without going into all the details, it boils down to the fact that there have been some challenges that conventional “one size fits all” CPU scalar processors don't solve that well. Plus, while very large vector processors (DSP, GPU) solve some problems, they also have some scaling challenges due to their inflexible, inefficient memory bandwidth usage. Traditional FPGAs provide a programmable memory hierarchy, but the traditional hardware development flow has been an obstacle to broad, high-volume adoption. The way to address these problems was to combine all three elements with a new tool flow that offers a variety of different abstractions—-from framework to C to RTL-level coding—-into what Xilinx calls an adaptive compute acceleration platform (ACAP).

 

Xilinx’s Versal™ ACAPs allow users to customize their own domain-specific architecture from these three programmable elements. It's a fully software-programmable, heterogeneous compute platform that combines three different architectures: Scalar Engines, Adaptable Engines, and Intelligent Engines. 

 

It delivers the best of all three architectures -- vector and scalar processing elements tightly coupled to programmable logic, all tied together with a high-bandwidth network-on-chip (NoC), which provides memory-mapped access to all three processing element types. This tightly coupled hybrid architecture allows a lot better customization and performance than any one implementation alone. The big deal is it can achieve performance improvements of up to 20X over today's fastest FPGA implementations and over 100X over today's fastest CPU implementations. It is expected to be used in data center, 5G wireless, and automotive driver assist applications.

 

My Very Own RoadTest in a Connected City Demo

Most people know me on element14 as the RoadTest Program Manager; in this role, I select products with the help of suppliers, like Avnet and Xilinx, to review (like the Ultra96, for instance), which I then give to select members who write detailed product reviews. But at XDF I had my own roadtest. let me tell you about it.

 

For most of XDF, I manned the element14 display at the Avnet booth, greeting attendees and telling them about the programs element14 offers. After the forum closed, I took some time to wander around before the displays were disassembled, taking a closer look at the exhibits, and collecting information for this article. On my journey, I found myself in the Alveo demo room and within a few minutes I was in the driver's seat of the Connected City Demo run by Algo-Logic Systems. At first I was a tad bit reluctant: the demo was a multi-monitor setup with numerous dashboards and a clever little car that I had to navigate in a virtual traffic world.

 

The demo itself consisted of Algo-Logic's (1) Black Diamond Rackmount (BDR-3) that reads data from multiple types of sensors, performs advanced signal processing, and time-stamps data with GPS using FPGA logic; (2) Algo's Key Value Store (KVS), which provides in-memory object store with extremely low latency and throughput performance to enable sensor fusion, real-time analytics, and scale out machine learning; (3) Xilinx Alveo U200 accelerator card, and (4) multiple dashboards. The BDR-3 collects live data from sensors in a connected city to monitor traffic conditions, wind and solar power generation, electric vehicle charging, infrastructure vibrations, thermal conditions, and drone control. The KVS fuses this live data and feeds it to multiple dashboards where it is charted and rendered to display the status and health of city-wide infrastructure in real-time. (How did I drive? Hmm...luckily, I didn't crash the car!)

 

Building the Adaptable Intelligent World

After the forum ended, on the flight home back to Chicago, I began writing this article. I had collected a lot of information, but I was drawn to my notes on Victor Peng's keynote address. It was entitled, "Building the Adaptable Intelligent World." As with most keynote speech titles or conference taglines, they are aspirational in nature. But "building an adaptable intelligent world" embodied more than futuristic aspiration; rather, it encompassed the Xilinx oeuvre and extended it with the ACAP introduction to give developers the hardware and tools to make the metaphoric "quantum leap" from aspiration to actualization. One can only wait patiently as developers across the world not only deploy the technology but also use it to solve the world's most pressing problems in healthcare, climate change, biodiversity reductions, and the pursuit of happiness. I can't wait!