So, last time I managed to get the SQL Acron CLE-215 running whilst powered by an external power supply and connect to it over JTAG. This let me get blinky running but didn't really take advantage of the unusual feature which drew me to the board - the PCIe interface. Now that I knew I had some control over the board it was time to put it inside my PC.

 

Hardware

My main desktop is a small-ish form factor machine running Windows 10. Luckily I had a slightly older tower PC that had much more room for PCIe board. Whilst the SQRL board isn't tall, that large heatsink does make it awkwardly wide. Talking of which, how would it ever be possible to put this in the m.2 slot of a laptop? It might just about fit with the heatsink removed, but I suspect that taking any advantage of the power of the onboard Artix-7 would cause it to overheat very quickly.

So I installed the SQRL board and its PCIe carrier inside the desktop. This wasn't too difficult but I didn't want to give up JTAG, so I have the rather strange configuration of a USB cable connected to the PC and snaking back inside where it connects to a Digilent HS2 JTAG programming cable that's taped to a convenient rail. Obviously the primary use case for this device is where your bitstream is loaded in from flash and you interact with it over PCIe. That's all fine once you've finished developing the PL, but I still need JTAG for a little while longer.

 

Software

I decided that to make things easier to work with PCIe drivers I would run Ubuntu natively on this machine. Most Xilinx PCIe examples start from Linux so I didn't want to make things harder than they needed to be. After a brief flirt with Ubuntu 20.04 LTS - because you know, it's new and shiny - I found out that Xilinx weren't joking when then said only 18.04 LTS is supported. I was tripped up by things like Petalinux builds that are unrelated to this board, but it still seemed wise to stick with what's supported by Xilinx for now.

 

Luckily the documentation for the NiteFury board included a PCIe example block design and some basic instructions for getting Xilinx's XDMA driver installed on Linux. The block design synthesis and was transferred over to the device without a problem. The driver side however was a little more tricky. I thought that Vivado was a bit touchy about versions, but the XDMA drivers were even more so. There were so many gotcha that required quite a bit of searching, and you have to wonder why some of this wasn't included in the Xilinx-supplied instructions.

 

Firstly, a signing key was missing so the drivers couldn't be compiled. I found the solution here, but it really should have been included. Things then got even stranger.

cd /usr/src/linux-headers-$(uname -r)/certs
sudo openssl req -new -x509 -newkey rsa:2048 -keyout signing_key.pem -outform DER -out signing_key.x509 -nodes -subj "/CN=Owner/"

 

 

The build got further but then complained about a missing 'System.map' file. More googling and rabbit holes later, it seems that not only is the version of Linux important, later kernels cause problems. I ended up having to revert the kernel on my Ubuntu 18.04 from 5.3 to 4.15. Considering I'm probably an 80% Windows / 20% Linux guy, altering the active kernel seems a bit out there. However, I managed it with the following:

sudo apt remove linux-image-5.3.0-59-generic
sudo apt remove linux-image-5.3.0-53-generic
sudo apt remove linux-image-unsigned-5.3.0-53-generic
sudo apt remove linux-image-5.3.0-28-generic
sudo update-grub
sudo reboot now

 

With the change in kernel (and hence the value returned by "uname -r") I had to redo the SSL cert above. I could now build the kernal module and install it!

 

Next is a quick test of communication between Linux and the FPGA. Unfortunately Linux is still not happy with the XDMA drivers. A lot of searching has yet to come up with a solution to this. There are other avenues I can explore, such as using Xilinx QDMA drivers under Windows btu considering that would need a whole OS reinstallation. Time constraints and other things I need to do (like a job) mean I will unfortunately have to leave it here for now.

 

Summary

It was a bit of a gamble buying a totally undocumented and manufacturer-abandoned FPGA board on eBay. I've had a lot of fun reverse engineering things like JTAG and learned a lot along the way. In some ways, discovering the link between the SQRL Acorn and the NiteFury turned the potentially impossible into a much easier proposition.

 

Whilst I haven't had the time to really make use of the strengths of the device yet, I have managed to find £30-worth of eBay junk and make this into a $349 development board. Considering most Xilinx boards that support PCIe are in the 4-digit price range it seems even more of a bargain! Looking at the thread I started an EEVBlog and a few posts on Twitter from other FPGA developers, it seems that a few of these once useless cryptominer cards have now found a good home. It's great that I've not only saved this one from the e-waste pile but quite a few others too.

 

I think I'm going to all the end result of a nice dev board to be the final output of this project. The use of it for a PCIe-based project will have to wait for another day.