Abstract:  This ’blog is a new version of Flavia: The Free Logic Array, published July 2014.  There have been many improvements to Flavia since then, including Spartan-6 implementations for the LOGI-Pi, LOGI-Bone, and most recently for the new Papilio DUO.  A Flavia design can now include a I/O pin assignment table with optional configuration of pull-up, pull-down, and keeper circuits (only for the Papilio DUO right now).


This ’blog introduces the Papilio DUO implementation of Flavia and shows how to run it on a Raspberry Pi 2.  That board is powerful enough to be a viable platform for logic design using Flavia and the rest of my XXICC (21st Century Co-design) software.  To download Flavia and XXICC software, data files, and additional documentation, see XXICC (21st Century Co-design) release 0.0p.


The recently-introduced Raspberry Pi 2 is a major performance upgrade over its predecessor, the RasPi B+.  It’s actually powerful enough to act as a desktop computer: users have reported decent performance using browsers, document editing, spreadsheets, reading PDFs and other typical desktop applications.  This means RasPi 2 is a viable alternative to a power-hungry x86 PC with a noisy fan, except for one problem: there is still a lot of software out there that’s only available as x86 binaries, and it cannot run on a RasPi ARM processor except through slow x86 emulation.


A stark example of this is FPGA (Field-Programmable Gate Array) design software.  General-purpose FPGA design tools such as Xilinx’s free-as-in-beer ISE WebPack only run on an x86 PC that has fairly high performance.  Since Xilinx has never published the details of its bitstream format -- and frowns on efforts to reverse-engineer it -- there has never been a general-purpose open-source FPGA tool suite and thus no way to recompile Xilinx tools for ARM.


However, it’s not a completely lost cause, thanks to Flavia: The Free Logic Array.  Flavia is a family of logic arrays that can be designed and programmed entirely using Free-as-in-Liberty Open-Source Software (FLOSS).  Flavia is basically a CPLD implemented in an FPGA, where FPGA look-up tables (LUTs) are used both for logic functions and for building multiplexers to implement routing.  By changing the bit patterns in these LUTs, Flavia software can implement logic functions and the connections between them and external I/O pins.


Since Flavia is distributed as source code it can run on many computers including standard x86 PCs (both Windows and GNU/Linux) as well as single-board computers like RasPi, BeagleBoard/Bone, and the recently-introduced ODROID-C1.  While the tools work on RasPi 1 and Beagles, they are a lot slower than a typical x86 PC and it’s doubtful than a user would want to use those platforms.  However, an SBC with a quad-core ARM Cortex A7 or A5 like RasPi 2 or ODROID-C1 is fast enough that it makes a very nice FPGA development platform.


Before examining Flavia’s internal architecture and looking at some examples, we’d better take care of some legal fine print:

Disclaimers: The Flavia and XXICC software described in this ’blog are distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License www.gnu.org/licenses/gpl.html for details.


An incorrect FPGA bitstream could cause damage to an FPGA and/or its connected circuitry, or cause a system to malfunction.  Users must agree that the author(s) and copyright holder(s) of Flavia and XXICC software have NO LIABILITY for any damages.  See the GNU General Public License for details.


Flavia is not associated in any way with Xilinx Inc.  If you have problems with Flavia, please do not blame Xilinx and please don’t ask them for Flavia support.  Instead, go to xxicc.org and follow the links you find there.


Flavia does not provide a way to reverse-engineer Xilinx FPGAs other than Flavia itself.  The locations of FPGA look-up tables and flip-flops used by Flavia are from files openly documented by Xilinx, supplemented with suggestions provided by Xilinx engineering at forums.xilinx.com.  They are only useful for Flavia and do not endanger the security of other Xilinx-based designs.  This is described in detail in Taming the Wild Bistream.


Introduction to Flavia


This section is abridged from the original Flavia ’blog which has more detail if you’re interested.


Flavia was inspired by a great discussion on element14.com called Role for FPGA or CPLD with Raspberry Pi, specifically by an excellent question asked by morgaine.  The discussion is about the challenges of teaching about programmable logic and is quite interesting.


Flavia is designed for new FPGA designers who want to play with FPGA technology without having to climb the steep learning curve associated with an FPGA vendor’s tool suite.  Flavia arrays are fairly small, with the capabilities of a CPLD (Complex Programmable Logic Device) rather than a large FPGA.  Flavia is intended to be an easy and fun way to learn basic programmable logic design so that learning vendor tools won’t be as daunting.


Here are Flavia’s key advantages:


  1. Flavia tools can run on non-Intel architectures.  Specifically, they can run on ARM-based single-board computers like Raspberry Pi and BeagleBoard/Bone.

  2. Flavia tools are fast.  Compiling a small design and downloading it to an FPGA using the Xilinx ISE tools generally takes around a minute on a reasonably fast PC.  Flavia can compile and download a small design in less than a second on the same PC, or in 1-2 seconds on RasPi 2.

  3. Flavia tools are FLOSS (Free-as-in-Liberty Open-Source Software).  This means that you and the community can improve Flavia tools and adapt them to other purposes.  Tools are not limited to the capabilities provided by FPGA vendors.  Flavia is licensed under GPLv3.

  4. Flavia tools are small.  The entire source code including all of the XXICC (21st Century Co-design) software is about a megabyte.  In contrast, the Xilinx tools are gigabytes.

  5. Vendor tools generally require designs to be written in Verilog or VHDL.  Many people have found the languages difficult to learn and to use, though many people like one or both.  Chacun a son goût (YMMV).  There are books available to learn either language.

    Flavia uses the much simpler GalaxC extensions for Hardware Design (GCHD).  GCHD is similar to Verilog, but has (in the opinion of the author) cleaner syntax and semantics.

    Flavia tools also include a figure editor so designs can be drawn as logic diagrams.  Many vendor tool suites also include schematic editing.  Logic diagrams can be a great tool for learning about logic design, but once designs get complex most designers find an HDL is more useful.

    Since Flavia tools are FLOSS, you are not limited to GCHD as the only HDL.  You or the community can create or adapt compilers for any hardware description language or other scheme to create designs and then interface them into the Flavia tools.

Flavia does have disadvantages, which pretty much limits its use to learning about FPGAs and small projects with loose performance requirements.


  1. Flavia designs are small: Flavia provides the capabilities of a CPLD, not an FPGA.  This is because the multiplexers that route signals between logic functions consume most of the FPGA’s LUTs.  If you need lots of gates, use vendor tools.

  2. Flavia designs are much slower than FPGA implementations.  Again, this is because the routing is implemented using multiplexers, but also because the outputs of function blocks need to be routed throughout the FPGA.  If you need to meet specific timing requirements, use vendor tools.

  3. While you can use Flavia for any purpose, Flavia designs are not intended for final products.  They make very inefficient use of FPGA LUTs, and do not provide bitstream security if that’s important to you.  For products, use smaller, cheaper FPGAs or CPLDs, and vendor tools.

  4. Flavia designs have functional limitations.  For example, Flavia does not currently support bidirectional I/O pins and I/Os are limited to 3.3V LVTTL.  Flavia has only one clock for flip-flops, derived from the FPGA board’s 32 or 50 MHz oscillator.

  5. Flavia software is still young and there are plenty of rough edges and probably undetected bugs.  Some capabilities are preliminary.  For example, logic synthesis does not detect common sub-expressions so it’s up to the designer to enter efficient designs.

Even with these restrictions, you should find Flavia to be a good platform for learning about FPGAs.  Later releases will have improved capabilities.


FlaviaPD59 Architecture


We will now look at a specific Flavia implementation: FlaviaPD59 for the Gadget Factory Papilio DUO.  The DUO is Gadget Factory’s latest FPGA development board and has the following capabilities:


    1. Xilinx XC6SLX9 Spartan-6 FPGA, which is large enough for 60 6-input arbitrary function blocks (AFBs) with full input multiplexing.  We use 59 for FlaviaPD59.

    2. Atmel ATmega32U4 Arduino Leonardo-compatible processor, which connects to some of the FPGA pins so you can make projects that combine an FPGA and a microcontroller.  Flavia does not use this processor and holds it in reset so the FPGA can use the shared pins.

    3. 54 I/Os on 0.1" sockets, which are easy to interface with external circuits.  48 of the I/Os can be used with Papilio “wings”: Gadget Factory has a nice collection of inexpensive add-on boards such as the Button/LED Wing with 4 LEDs and 4 push-buttons, and a solderless Breadboard Wing for adding external ICs.  The sockets are also compatible with Arduino shields, and some of the I/Os connect to the ATmega32U4.

    4. FTDI FT2232H high-speed USB controller for programming the FPGA using JTAG.  FTDI is supported by the FLOSS library libftdi.so which provides I/O for sending bitstreams and other messages over USB.  Reprogramming the XC6SLX9 takes a few tenths of a second and is done directly from the Flavia tools without having to run a separate program.

      (There’s also a free-as-in-beer Microsoft Windows driver, provided by FTDI.  RasPi 2 uses libftdi.so.)

      The FT2232H has a second serial port connected to five FPGA pins so that a host computer can talk to the FPGA as a USB serial port.  FlaviaPD59 connects to these five pins.

    5. 512 KB or 2 MB asynchronous SRAM connected to the FPGA.  Flavia does not use the SRAM.


In the author’s opinion, Gadget Factory has a nice business model with open-source hardware and a friendly forum for answering questions.


Here is the high-level block diagram for FlaviaPD59:

FlaviaPD59 Architecture

FlaviaPD59 consists of 59 identical AFBs, each connected to an FPGA I/O pin.  D0-D53 connect to DUO’s 0.1" socket headers.  The pin numbering corresponds to Arduino shields.  D0-D53 are named MEGA_D0 through MEGA_D53 on the Papilio DUO schematic or D0-D53 on the Papilio DUO Pinout Diagram.  They are labeled 0-53 on the Papilio DUO PC board:

Papilio DUO top side

D0-7 and D14-53 are also used by Papilio wings AL, BL, CL, CH, DL, and DH.  Each wing has 4 power pins and 8 I/O pins, arranged in two rows.  The PCB shows wing names in 6-sided blocks: for example, “AL” is just below pins D5-D2.  (The labels might be clearer in the photo further down the page.)   Wing I/O pins are named AL0-AL7, BL0-BL7, CL0-CL7, CH0-CH7, DL0-DL7, and DH0-DH7.  Gadget Factorys Papilio DUO Pinout Diagram shows the mapping between D0-D53 and wing pin numbers.  Flavia software implements this mapping so you can use either set of names for your FlaviaPD59 designs.


BD0-BD4 connect to the FT2232H’s second serial port.  In addition there is a dedicated input pin SW1 connected to DUO’s slide switch.  See the Papilio DUO schematics for details.


Except for input SW1, each I/O can be either an input or an output.  (Flavia software does not currently support bidirectional pins, though the FlaviaPD59 hardware does.)  Each AFB implements an arbitrary 6-input Boolean function and has a D flip-flop (DFF).  Each of the six inputs can come from any I/O pin.  Each horizontal line on the left side of the diagram represents a 60:1 (60-to-1) multiplexer, with each possible input shown as ‘x’.


In addition, each AFB has a set/reset (sr) input which is the asynchronous init signal for the AFB’s DFF, and an output disable (od) input which controls whether the AFB’s pin is an input or an output.  FlaviaPD59 I/O pins have programmable internal pull-up, pull-down, and keeper circuits.  Unused pins are pulled high.


Each AFB needs eight 60:1 multiplexers, implemented using LUTs.  Here is the block diagram for one of these multiplexers:

Flavia 60:1 Multiplexer

The 60:1 multiplexer takes advantage of a nice feature of Spartan-6 LUTs: a 6-input LUT can do a single 6-input logic function, or it can do two 5-input logic functions provided that they share the same five input signals.  Each of the six LUT5s selects one of five inputs.  The second-level LUT6 selects one of six inputs, giving us a 30:1 multiplexer.  Flavia can program a LUT with a single-input logic function that passes one of the inputs -- perhaps inverted -- and ignores the rest.  Alternatively, Flavia can program a LUT with all zeros or all ones to produce a 0 or 1 output and ignore all inputs.  The two 30:1 multiplexers are combined using a 2:1 mux built into the Spartan-6 logic block.  This 2:1 mux is in addition to the LUTs and has very fast local connections that add minimal delay to the 60:1 mux.


The select line for the 2:1 mux is FF cfg0 which is in the same logic cell as the LUT6es.  Basically, to program a 60:1 multiplexer to select one of the 60 inputs, Flavia sets one LUT5 and one LUT6 to a single-input function and the rest of the LUTs to all zeroes, and then sets cfg0 to select the LUT6.


So, how does Flavia program these LUTs and FFs?  Well, each LUT and FF is in a well-defined location in the Xilinx bitstream.  Normally, Xilinx does not give you the bitstream format, but they make an exception for LUTs and FFs.  This is primarily so you can read back the FPGA bitstream and get the current values of LUTs (which can be used as RAMs) and FFs, but the information provided by Xilinx lets you write your own values into those locations.  Flavia simply takes a generic Flavia bitstream (FlaviaPD59.bit), writes the LUT and FF values required for each 60:1 mux into the proper locations in the bitstream, calculates a new checksum, and downloads the result into Papilio over the USB connection.  All this takes RasPi 2 less than two seconds.


Now that we have 60:1 muxes worked out, let’s take a look at the 6-input AFB.  Here’s the block diagram:

Flavia AFB for Spartan-6

The LUT6 calculates an arbitrary 6-input Boolean function of the six inputs p0-p5.  An AFB’s output can be the output of the 6-input function -- i.e, combinational logic (C/L) -- or the value of the DFF which is updated by the rising edge of a shared Flavia clock.  We use a LUT as a multiplexer to support future applications.  There is also a feedback mux to route the LUT6 output or DFF state back to the 60:1 multiplexer array so it doesn’t have to go through the pin.  FlaviaPD59 logic functions do not drive pins unless they’re explicitly defined as outputs.  This prevents externally-attached circuits from misbehaving if driven unintentionally.


The DFF has an asynchronous init signal sr which sets the DFF to 1 or 0, configured by Flavia software.  Xilinx FFs have clock enable inputs, but FlaviaPD59 doesn’t use them: AFB FF clocks are always enabled.


As you can see, FlaviaPD59 has a very simple architecture which means that synthesis tools can be simple.  All AFBs are identical, and there are no routing restrictions so Flavia software can assign any 6-input function to any AFB, restricted only by how the user wants to assign pins to Papilio I/O sockets.


There are a number of improvements planned for future releases, and we hope others will be suggested by the community.  For example, the AFB output LUT can implement some logic functions like detecting a state change.  A major improvement is to replace each 60:1 multiplexer with a 60-input AND gate or OR gate with invertible inputs, i.e., a minterm or maxterm.  This can significantly improve Flavia’s logic capacity with a modest increase in software complexity.


Using FlaviaPD59


You can create Flavia designs using GCHD (GalaxC for Hardware Design) text, logic diagrams, or a combination.  The two examples in this section will give you an overview of both.


Example 1: 4-bit Binary Counter


The first design is a 4-bit binary counter written in GCHD.  While it’s mostly plain text, Bcount4PD.xoe also includes a table so it must be edited using the XXICC Object Editor (XOE).


// Bcount4PD.xoe: 4-bit binary counter for Papilio DUO.


include "gchd.gi";      // This line is needed for GCHD designs.


synthesis pinout        // Assign signals to Papilio DUO pins.

signalpinoptions  // and comments.
resetDH7// PB1: press to reset counter.
up~DH5// PB2: press to hold counter, count up if released.
s3DH6// LED1 = MSb. 
s2DH4// LED2 = MSb-1.
s1DH2// LED3 = LSb+1.
s0DH0// LED4 = LSb.   


synthesize hardware (target = FlaviaPD59, clk = 4)

// 4-bit binary up-counter.

    clock net clk;          // Flavia clock (default = 2 Hz).

    net reset;              // Reset counter if high, otherwise enable counter.

    net up;                // Count up if !reset and up, otherwise hold.

    reg {s3, s2, s1, s0};  // Counter state.

    // If reset, asynchronously reset s3-s0.

    if reset then s3 = s2 = s1 = s0 = FALSE else

    if clk rises then

    {  // On rising clk, increment s3-s0 if up, otherwise hold s3-s0.

        s3 ^= up & s2 & s1 & s0;

        s2 ^= up & s1 & s0;

        s1 ^= up & s0;

        s0 ^= up;




Bcount4PD.xoe begins by including the GCHD library “gchd.gi”, which is required for all GCHD designs.  Next we have the synthesis pinout table which assigns your design’s top-level input and output signals to Papilio DUO pin names.  The first row must have column headings “signal”, “pin”, and “options” if the third column is present.  Bcount4PD.xoe only uses the options column for comments, each preceded by “//”.


The synthesize hardware statement describes the counter.  This example is a flat, non-hierarchical design so all the logic is in a single top-level module.  GCHD uses the term net to mean an unregistered, unlatched signal.  Verilog calls nets “wires”.  A reg is an edge-triggered register or a latch.  Undriven nets like reset and up are top-level inputs.  All other signals are outputs or internal.


reset” is an asynchronous init signal that connects to AFB sr inputs and sets the counter state s3-s0 to 0000.  “up” allows the counter to increment once per clock if reset = 0.  “clk” is the Flavia clock derived from the Papilio DUO’s 32 MHz oscillator by dividing by an integer from 1 to 32,000,000.  The default Flavia clock is 2 Hz, but we have set it to 4 Hz using a synthesize hardware option.  The Flavia clock is built in and does not use any of the Flavia AFBs or I/Os.


GCHD uses the compact C notation “s3 ^= up & s2 & s1 & s0” to toggle state bit s3.  This is equivalent to “s3 = s3 ^ (up & s2 & s1 & s0)” where ‘^’ is the exclusive-or operator.  The statement toggles s3 at the rising edge of clk iff s2 = s1 = s0 = 1 and up = 1.  The other state update statements are similar.


The synthesis pinout table assumes a Gadget Factory Button/LED Wing is plugged into the DH pins, like this:

Papilio DUO with Button/LED wing

This Papilio DUO is black because it’s the Kickstarter Edition.

The counter state s3-s0 is displayed in LED1-LED4 and push buttons PB1 and PB2 are reset and ~up.  Here is the Button/LED pinout:


  PB1  LED1  PB2  LED2  PB3  LED3  PB4  LED4


Button/LED Wing LEDs turn on when LED1-LED4 are high.  PB1-PB4 are high when buttons are pressed and pulled low when released.  In the synthesis pinout table, we want to reset when PB1 is pressed so reset is assigned to non-inverted DH7.  On the other hand, we want to count unless PB2 is pressed, so up is assigned to inverted DH5.  If PB2 is released, ~DH5 is true and up = 1, allowing the counter to count: PB2 is a “hold” button which inhibits counting.


Compiling and Running a Flavia Design


To run the examples you will first need to install XXICC on your RasPi 2.  See Installing and Running XXICC rev 0.0p for instructions.  You will also need to unzip FlaviaPD59-00p.zip [Data files for FlaviaPD59 release 0.0p and 0.0q] in your XXICC directory.  This has the files Flavia needs to synthesize logic for FlaviaPD59, along with source code for the examples.


You also need to connect your Papilio DUO to a RasPi 2 USB port using a USB A to Mini B cable.  This cable powers Papilio DUO and talks to the FT2232H.  Be sure to plug into the Mini B port, labeled “FPGA USB”.  The Micro USB port “AVR USB” talks to the ATmega32U4.  Also, be sure there is a jumper installed on the “PWRSEL” header.  It should connect the middle pin to the “FPGA” pin so that the Papilo DUO is powered from the Mini B cable.


When you plug in your Papilio DUO the red “PWR” LED should come on.  If there is a valid FPGA bitstream in the DUO’s Flash chip, it will automatically load within a few seconds.  On my DUO there’s a manufacturing test program that causes I/O pins to toggle.  Papilio DUO has hard wired the FPGA’s configuration mode so it always tries to load from Flash.  This is annoying, but isn’t a problem for the examples in this ’blog. 


To run the 4-bit counter example, switch to the directory in which you installed XXICC and unzipped FlaviaPD59-00p.zip and start it up with the fla option:


./xxicc fla


XXICC should load the XXICC object code compiled previously for Flavia and link to libftdi.so.  XXICC should also install FlaviaPD59 as a synthesis target.


When XXICC completes loading, it will bring up a file selection dialog.  Open “Bcount4PD.xoe”.  You are now in the XXICC Object Editor, or XOE.  Compile the example by pressing F6.  GalaxC should compile the example, synthesize Flavia logic, and download the resulting bitmap to your Papilio DUO, all in 1-2 seconds on RasPi 2.


The counter should begin counting immediately, updating four times a second.  If you press PB1, s3-s0 resets to 0000 and counts from 0000 when you release PB1.  If you press PB2, s3-s0 stops at its current state and resumes counting when you release PB2.


Example 2: 9-input Tally Circuit


The second example is a 9-input Tally circuit drawn as logic diagrams.  It counts the number of TRUE inputs and expresses the tally as a 4-bit binary number from 0000 to 1001.  The Tally circuit (shown below) is a hierarchical design with three modules: FADD is a full adder which adds binary inputs a, b, and c to produce a 2-bit binary sum <t, s> with value 00, 01, 10, or 11.  HADD is a half adder which adds binary inputs a and b to produce a 2-bit binary sum <t, s> with value 00, 01, or 10.  Tally9 adds binary inputs a-j to produce a 4-bit binary sum y3-y0.  It uses full adders to reduce a-j to two binary numbers and then adds them using a ripple-carry adder constructed from one HADD and one FADD.


// tally9PD.xoe: 9-input tally circuit for Papilio DUO.


include "gchd.gi";


module FADD =

Full Adder

module HADD =

Half Adder

module Tally9 =

9-input Tally Circuit

synthesis pinout    // Assign signals to Papilio DUO pins.

y3DH6// LED1 = MSb 
y2DH4// LED2 = MSb-1
y1DH2// LED3 = LSb+1
y0DH0// LED4 = LSb   
aDH1// Push button 4
bDH3// Push button 3
cDH5// Push button 2
dDH7// Push button 1


synthesize hardware (target=FlaviaPD59) Tally9


Tally9PD.xoe begins by including the GCHD library gchd.gi.  Next we have the module definitions for FADD, HADD, and Tally9.  Next we have the synthesis pinout for a Gadget Factory Button/LED Wing plugged into the DH pins.  The pinout table assigns outputs y3-y0 to LED1-LED4 and inputs a-d to buttons PB1-PB4.  We also need to assign pins to inputs e-j.  Rather than hooking up more buttons, we use the options column to configure internal pullup resistors for e-g and pulldown resistors for h-j.  These pullup and pulldown resistors are in the Spartan-6 FPGA.  Each has a value of approximately 10KΩ.


You can override the pullup/down resistors by hooking up external wires to pull e-j to +3.3V or GND, preferably through a 100Ω resistor.


To run this example, start up XXICC as with the previous example and open “Tally9PD.xoe”.  Compile the example by pressing F6.  GalaxC should compile the example, synthesize Flavia logic, and download the resulting bitmap to your Papilio DUO, all in 1-2 seconds.


The LEDs should immediately show the value 0011 since e-g are pulled up and all others are pulled down.  The Button/LED Wing has pull-down resistors for PB1-PB4, which set PB1-PB4 to 0 if no buttons are pressed.  If you press PB1, a = 1 and the LEDs change to 0100.  Pressing PB2-PB4 in addition to PB1 gives count values 0101, 0110, or 0111 depending on how many buttons are pressed.  You can also change the pullup/down options for e-j to set the value of y3-y0 when no buttons are pressed.  Recompile using F6; saving before recompiling is optional.  Recompilation and reloading the FPGA takes 1-2 seconds for this simple design, which is much faster than Xilinx tools.


Basically, that’s all there is to using Flavia once you have learned about XOE and GCHD.  For details on those, see The XXICC Anthology rev 0.0n Chapters 2, 8, and 10.  For more details on using Flavia and how it is implemented, see Chapter 12.  (Rev 0.0n does not include the Papilio DUO or synthesis pinout.  This will be fixed in a later revision.)


Flavia is a work in progress and we have many plans for the near future, including:


  1. Adding configurable pull-up, pull-down, and keeper to all Flavia implementations’ I/O pins.  Currently FlaviaPD59 for the Papilio DUO is the only implementation with configurable I/Os.

  2. Improving FlaviaP32 and P48 for the Papilio One boards based on Spartan-3E FPGAs.  We should be able to upgrade FlaviaP32 to FlaviaP40 with 40 AFBs and FlaviaP48 to FlaviaP56 with 56 AFBs.  Also, FlaviaP32 and P48 feed back outputs through I/O pins even if the signal is not declared as an output.  This slows feedback signals and may cause unintended signals on I/O pins.  We can fix this by adding multiplexer LUTs as with the Spartan-6 AFB.

  3. Adding dedicated outputs to FlaviaLP56, LB56, and PD59.  They will become FlaviaLP60, LB60, and PD60.

  4. Implementing integer signals and operators in GCHD.  Currently Flavia only allows Boolean signals which limits it to simple examples.  Using integer operators like add, subtract, and compare as well as multiplexing of integers will greatly simplify GCHD source code for many designs.


Now all I need is the time to implement all these wonderful features


This document is licensed under the Creative Commons Attribution-ShareAlike 3.0 Unported License.  To view a copy of this license, visit creativecommons.org/licenses/by-sa/3.0/.  No warranty is expressed or implied.  Raspberry Pi is a trademark of the Raspberry Pi Foundation.  Flavia, XXICC, and GalaxC are trademarks of John F. Beetem.